eMachines EL1800 Service Guide - Page 54

Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the POSTINT1Ch

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Checkpoint FB F4 FC FD FF 03 04 05 06 07 08 C0 C1 C2 C5 C6 C7 0A 0B 0C 0E 13 20 24 2A 2C Description Make flash write enabled through chipset and OEM specific method. Detect proper flash part. Verify that the found flash part size equals the recovery file size. The recovery file size does not equal the found flash part size. Erase the flash part. Program the flash part. The flash has been updated successfully. Make flash write disabled. Disable ATAPI hardware. Restore CPUID value back into register. Give control to F000 ROM at F000:FFF0h. Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Runtime data area. Also initialize BIOS modules on POST entry and GPNV area. Initialized CMOS as mentioned in the Kernel Variable "wCMOSFlags." Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is bad, update CMOS with power-on default values and clear passwords. Initialize status register A. Initializes data variables that are based on CMOS setup questions. Initializes both the 8259 compatible PICs in the system Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table. Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch vector to "POSTINT1ChHandlerBlock." Fixes CPU POST interface calling pointer. Initializes the CPU. The BAT test is being done on KBC. Program the keyboard controller command byte is being done after Auto detection of KB/MS using AMI KB-5. Early CPU Init Start -- Disable Cache - Init Local APIC. Set up boot strap processor Information Set up boot strap processor for POST Enumerate and set up application processors Re-enable cache for boot strap processor Early CPU Init Exit Initializes the 8042 compatible Key Board Controller. Detects the presence of PS/2 mouse. Detects the presence of Keyboard in KBC port. Testing and initialization of different Input Devices. Also, update the Kernel Variables. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1. Uncompress all available language, BIOS logo, and Silent logo modules. Early POST initialization of chipset registers. Relocate System Management Interrupt vector for all CPU in the system. Uncompress and initialize any platform specific BIOS modules. GPNV is initialized at this checkpoint. Initializes different devices through DIM. See DIM Code Checkpoints section of document for more information. Initializes different devices. Detects and initializes the video adapter installed in the system that have optional ROMs. 48

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48
Checkpoint
Description
FB
Make flash write enabled through chipset and OEM specific method. Detect proper flash
part. Verify that the found flash part size equals the recovery file size.
F4
The recovery file size does not equal the found flash part size.
FC
Erase the flash part.
FD
Program the flash part.
FF
The flash has been updated successfully. Make flash write disabled. Disable ATAPI
hardware. Restore CPUID value back into register. Give control to F000 ROM at
F000:FFF0h.
03
Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Runtime
data area. Also initialize BIOS modules on POST entry and GPNV area. Initialized CMOS
as mentioned in the Kernel Variable "wCMOSFlags."
04
Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is
OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is
bad, update CMOS with power-on default values and clear passwords. Initialize status
register A.
Initializes data variables that are based on CMOS setup questions. Initializes both the 8259
compatible PICs in the system
05
Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table.
06
Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the POSTINT1Ch
handler. Enable IRQ-0 in PIC for system timer interrupt.
Traps INT1Ch vector to "POSTINT1ChHandlerBlock."
07
Fixes CPU POST interface calling pointer.
08
Initializes the CPU. The BAT test is being done on KBC. Program the keyboard controller
command byte is being done after Auto detection of KB/MS using AMI KB-5.
C0
Early CPU Init Start -- Disable Cache – Init Local APIC.
C1
Set up boot strap processor Information
C2
Set up boot strap processor for POST
C5
Enumerate and set up application processors
C6
Re-enable cache for boot strap processor
C7
Early CPU Init Exit
0A
Initializes the 8042 compatible Key Board Controller.
0B
Detects the presence of PS/2 mouse.
0C
Detects the presence of Keyboard in KBC port.
0E
Testing and initialization of different Input Devices. Also, update the Kernel Variables.
Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1.
Uncompress all available language, BIOS logo, and Silent logo modules.
13
Early POST initialization of chipset registers.
20
Relocate System Management Interrupt vector for all CPU in the system.
24
Uncompress and initialize any platform specific BIOS modules. GPNV is initialized at this
checkpoint.
2A
Initializes different devices through DIM.
See DIM Code Checkpoints section of document for more information.
2C
Initializes different devices. Detects and initializes the video adapter installed in the system
that have optional ROMs.