AMD ADA3800DAA5BV Product Data Sheet - Page 1

AMD Athlon™ X2 Dual-Core Processor Product Data Sheet • Compatible with Existing 32-Bit Code Base • Power Management - Including support for SSE, SSE2, SSE3, MMX™, - Multiple low-power states including C1E 3DNow!™ technology and legacy x86 instructions - System Management Mode (SMM) - Runs existing operating systems and drivers - ACPI-compliant, including support for processor - Local APIC on-chip performance states • AMD64 Technology - AMD64 technology instruction set extensions - 64-bit integer registers, 48-bit virtual addresses, 40-bit physical addresses Socket AM2 Specific Features - Eight additional 64-bit integer registers (16 total) - Eight additional 128-bit SSE/SSE2/SSE3 registers • Refer to the Socket AM2 Processor Functional (16 total) Data Sheet, order# 31117, for functional and mechanical details of socket AM2 processors. • Dual-Core Architecture - Discrete L1 and L2 cache structures for each core • Refer to the AMD NPT 0Fh Family Processor Electrical Data Sheet, order# 31119, for • HyperTransport™ Technology to I/O Devices electrical details of socket AM2 processors. - One 16-bit link supporting speeds up to 1 GHz (2000 • Electrical Interfaces MT/s) or 4 Gigabytes/s in each direction - HyperTransport™ technology: LVDS-like • 64-Kbyte 2-Way Associative ECC-Protected differential, unidirectional L1 Data Caches - DDR2 SDRAM: SSTL_1.8 per JEDEC - Two 64-bit operations per cycle, 3-cycle latency specification • 64-Kbyte 2-Way Associative Parity-Protected L1 Instruction Caches - Clock, reset, and test signals also use DDR2 SDRAM-like electrical specifications - With advanced branch prediction • Packaging • 16-Way Associative ECC-Protected - Lidded micro PGA L2 Caches - 31 x 31 grid array - Exclusive cache architecture-storage in addition - 1.27-mm pin pitch to L1 caches - Compliant with RoHS (EU Directive 2002/95/EC) - Up to 1 Mbyte per L2 cache with lead used only in small amounts in specifically exempted applications • Machine Check Architecture - Includes hardware scrubbing of major • Integrated Memory Controller ECC-protected arrays - Low-latency, high-bandwidth - 144-bit DDR2 SDRAM controller operating at up to 400 MHz - Supports up to four unbuffered DIMMs - ECC checking with double-bit detect and single-bit correct Publication # 43042 Issue Date: May 2007 Revision: 3.00 Advanced Micro Devices