ASRock A320M-HDV R3.0 User Manual - Page 59

TwrwrDd, TrdrdSc, TrdrdSd, TrdrdDd, ProcODT, Data Bus Configuration, Gear Down Mode, Power Down

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Page 59 highlights

TwrwrDd The minimum number of cycles from the last clock of virtual CAS of the first write-burst operation to the clock in which CAS is asserted for a following write-burst operation in a different DIMM. TrdrdSc The minimum number of cycles from the last clock of virtual CAS of the first read-burst operation to the clock in which CAS is asserted for a following read-burst operation in the same chipselect. TrdrdSd The minimum number of cycles from the last clock of virtual CAS of the first read-burst operation to the clock in which CAS is asserted for a following read-burst operation in the same DIMM. TrdrdDd The minimum number of cycles from the last clock of virtual CAS of the first read-burst operation to the clock in which CAS is asserted for a following read-burst operation in a different DIMM. tCKE Specifies the CKE minimum high and low pulse width in memory clock cycles. ProcODT Specifies the Processor ODT Data Bus Configuration Configure the RttNom, RttWr and RttPark. Gear Down Mode Power Down Enable CAD Bus Configuration Command Rate (CR) The delay between when a memory chip is selected and when the first active command can be issued. 54 English

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English
54
TwrwrDd
°e minimum number of cycles from the last clock of virtual CAS of the first write-burst
operation to the clock in which CAS is asserted for a following write-burst operation in a
different DIMM.
TrdrdSc
°e minimum number of cycles from the last clock of virtual CAS of the first read-burst
operation to the clock in which CAS is asserted for a following read-burst operation in the
same chipselect.
TrdrdSd
°e minimum number of cycles from the last clock of virtual CAS of the first read-burst
operation to the clock in which CAS is asserted for a following read-burst operation in the
same DIMM.
TrdrdDd
°e minimum number of cycles from the last clock of virtual CAS of the first read-burst
operation to the clock in which CAS is asserted for a following read-burst operation in a
different DIMM.
tCKE
Specifies the CKE minimum high and low pulse width in memory clock cycles.
ProcODT
Specifies the Processor ODT
Data Bus Configuration
Configure the RttNom, RttWr and RttPark.
Gear Down Mode
Power Down Enable
CAD Bus Configuration
Command Rate (CR)
°e delay between when a memory chip is selected and when the first active command can
be issued.