ASRock A520M-HDVP User Manual - Page 50
Infinity Fabric Frequency and Dividers, CLD0 VDDG CCD Voltage Control
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A520M-HDVP derived from your DRAM Voltage (VDDIO_Mem). As a result, VDDP voltage in mV can approach but not exceed your DRAM Voltage. CLD0 VDDG CCD Voltage Control AMD Overclocking Setup VDDG CCD represents voltage for the data portion of the Infinity Fabric. It is derived from the CPU SoC/Uncore Voltage (VDD_SOC). VDDG can approach but not exceed VDD_SOC. CLD0 VDDG IOD Voltage Control AMD Overclocking Setup VDDG IOD represents voltage for the data portion of the Infinity Fabric. It is derived from the CPU SoC/Uncore Voltage (VDD_SOC). VDDG can approach but not exceed VDD_SOC. DRAM Information Load XMP Setting Load XMP settings to overclock the memory and perform beyond standard specifications. DRAM Frequency If [Auto] is selected, the motherboard will detect the memory module(s) inserted and assign the appropriate frequency automatically. Setting DRAM Frequency can adjust DRAM Timing. Infinity Fabric Frequency and Dividers AMD Overclocking Setup Set Infinity Fabric frequency (FCLK). Auto: FCLK = MCLK. Manual: FCLK must be less than or equal to MCLK for best performance in most cases. Latency penalties are incurred if FCLK and MCLK are mismatched, but sufficiently high MCLK can negate or overcome this penalty. DRAM Timing Configuration External Voltage Settings +1.8 Voltage Configure the voltage for +1.8. DRAM Voltage Use this to configure DRAM Voltage. The default value is [Auto]. VDDP Configure the voltage for the VDDP. 45 English