ASRock B150M-ITX User Manual - Page 43

DRAM Frequency OC Preset

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DRAM Tweaker Fine tune the DRAM settings by leaving marks in checkboxes. Click OK to conirm and apply your new settings. DRAM Timing Coniguration Load XMP Setting Load XMP settings to overclock the memory and perform beyond standard speciications. DRAM Reference Clock Select Auto for optimized settings. DRAM Frequency If [Auto] is selected, the motherboard will detect the memory module(s) inserted and assign the appropriate frequency automatically. DRAM Frequency OC Preset If the DRAM frequency is selected, the corresponding DRAM and BCLK frequency for overclocking will be set. Primary Timing CAS# Latency (tCL) he time between sending a column address to the memory and the beginning of the data in response. RAS# to CAS# Delay and Row Precharge (tRCDtRP) O RAS# to CAS# Delay : he number of clock cycles required between the opening of a row of memory and accessing columns within it. Row Precharge: he number of clock cycles required between the issuing of the precharge command and opening the next row. RAS# Active Time (tRAS) he number of clock cycles required between a bank active command and issuing the precharge command. Command Rate (CR) he delay between when a memory chip is selected and when the irst active command can be issued. Secondary Timing 38 English

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38
English
DRAM Tweaker
Fine tune the DRAM settings by leaving marks in checkboxes. Click OK to con±rm and
apply your new settings.
DRAM Timing Con±guration
Load XMP Setting
Load XMP settings to overclock the memory and perform beyond standard speci±cations.
DRAM Reference Clock
Select Auto for optimized settings.
DRAM Frequency
If [Auto] is selected, the motherboard will detect the memory module(s) inserted
and assign the appropriate frequency automatically.
DRAM Frequency OC Preset
If the DRAM frequency is selected, the corresponding DRAM and BCLK frequency for
overclocking will be set.
Primary Timing
CAS# Latency (tCL)
He time between sending a column address to the memory and the beginning of the data
in response.
RAS# to CAS# Delay and Row Precharge (tRCDtRP) O
RAS# to CAS# Delay : He number of clock cycles required between the opening of
a row of memory and accessing columns within it.
Row Precharge: He number of clock cycles required between the issuing of the
precharge command and opening the next row.
RAS# Active Time (tRAS)
He number of clock cycles required between a bank active command and issuing the
precharge command.
Command Rate (CR)
He delay between when a memory chip is selected and when the ±rst active command can
be issued.
Secondary Timing