ASRock B550 Taichi Razer Edition User Manual - Page 80

External Voltage Settings and Load-line Calibration

Page 80 highlights

B550 Taichi Razer Edition DRAM Information Load XMP Setting Load XMP settings to overclock the memory and perform beyond standard specifications. DRAM Frequency If [Auto] is selected, the motherboard will detect the memory module(s) inserted and assign the appropriate frequency automatically. Setting DRAM Frequency can adjust DRAM Timing. DRAM Voltage Configure the voltage for the DRAM Voltage. Infinity Fabric Frequency and Dividers AMD Overclocking Setup Set Infinity Fabric frequency (FCLK). Auto: FCLK = MCLK. Manual: FCLK must be less than or equal to MCLK for best performance in most cases. Latency penalties are incurred if FCLK and MCLK are mismatched, but sufficiently high MCLK can negate or overcome this penalty. DRAM Timing Configuration External Voltage Settings and Load-line Calibration Voltage Mode [OC] If this option is selected, there is larger range voltage for overclocking. [Normal] If this option is selected, there is smaller range voltage for normal system. CPU Core/Cache Voltage Input voltage for the processor by the external voltage refulator. CPU Core/Cache Load-Line Calibration CPU Core/Cache Load-Line Calibration helps prevent CPU voltage droop when the system is under heavy loading. CPU VDDCR_SOC Voltage Configure the voltage for the VID-requested VDDCR_SOC supply level. 73 English

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English
73
B550 Taichi Razer Edition
DRAM Information
Load XMP Setting
Load XMP settings to overclock the memory and perform beyond standard
specifications.
DRAM Frequency
If [Auto] is selected, the motherboard will detect the memory module(s) inserted
and assign the appropriate frequency automatically. Setting DRAM Frequency can
adjust DRAM Timing.
DRAM Voltage
Configure the voltage for the DRAM Voltage.
Infinity Fabric Frequency and Dividers
AMD Overclocking Setup Set Infinity Fabric frequency (FCLK). Auto: FCLK =
MCLK. Manual: FCLK must be less than or equal to MCLK for best performance in
most cases. Latency penalties are incurred if FCLK and MCLK are mismatched, but
sufficiently high MCLK can negate or overcome this penalty.
DRAM Timing Configuration
External Voltage Settings and Load-line Calibration
Voltage Mode
[OC]
If this option is selected, there is larger range voltage for overclocking.
[Normal]
If this option is selected, there is smaller range voltage for normal system.
CPU Core/Cache Voltage
Input voltage for the processor by the external voltage refulator.
CPU Core/Cache Load-Line Calibration
CPU Core/Cache Load-Line Calibration helps prevent CPU voltage droop when the
system is under heavy loading.
CPU VDDCR_SOC Voltage
Configure the voltage for the VID-requested VDDCR_SOC supply level.