ASRock B560M-HDV-A R2.0 User Manual - Page 59
ASRock Second Timing Optimization
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B560M-HDV-A R2.0 ODT PARK (B1) Configure the memory on die termination resistors' PARK for channel B1. COMP Setting Dll Bandwidth 0 Configure Dll Bandwidth 0 (1067 MHz) to maximize the performance of intergrated memory controller. Dll Bandwidth 1 Configure Dll Bandwidth 1 (1333 MHz) to maximize the performance of intergrated memory controller. Dll Bandwidth 2 Configure Dll Bandwidth 2 (1600 MHz) to maximize the performance of intergrated memory controller. Dll Bandwidth 3 Configure Dll Bandwidth 3 (1867 MHz) to maximize the performance of intergrated memory controller. Advanced Setting ASRock Timing Optimization Configure the fast path through the MRC. ASRock Second Timing Optimization Configure the second fast path through the MRC. Memory Training Mode Configure the Training Memory Mode. Realtime Memory Timing Configure the realtime memory timings. [Enabled] The system will allow performing realtime memory timing changes after MRC_DONE. Reset for MRC Failed Reset system after MRC training is failed. 53 English