ASRock Fatal1ty E3V5 Performance Gaming/OC User Manual - Page 63
tWRRD_dr, tWRWR_sg, RTL CH A, IO-L CH A, Fourth Timing, twRPRE, Write_Early_ODT
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Fatal1ty E3V5 Performance Gaming/OC Series Configure between module write to read delay. tWRRD_dr Configure between module write to read delay. tWRRD_dd Configure between module write to read delay. tWRWR_sg Configure between module write to write delay. tWRWR_dg Configure between module write to write delay. tWRWR_dr Configure between module write to write delay. tWRWR_dd Configure between module write to write delay. RTL (CH A) Configure round trip latency for channel A. RTL (CH B) Configure round trip latency for channel B. IO-L (CH A) Configure IO latency for channel A. IO-L (CH B) Configure IO latency for channel B. Fourth Timing twRPRE Configure twRPRE. Write_Early_ODT Configure Write_Early_ODT. 55 English
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English
Fatal1ty E3V5 Performance Gaming/OC Series
Configure between module write to read delay.
tWRRD_dr
Configure between module write to read delay.
tWRRD_dd
Configure between module write to read delay.
tWRWR_sg
Configure between module write to write delay.
tWRWR_dg
Configure between module write to write delay.
tWRWR_dr
Configure between module write to write delay.
tWRWR_dd
Configure between module write to write delay.
RTL (CH A)
Configure round trip latency for channel A.
RTL (CH B)
Configure round trip latency for channel B.
IO-L (CH A)
Configure IO latency for channel A.
IO-L (CH B)
Configure IO latency for channel B.
Fourth Timing
twRPRE
Configure twRPRE.
Write_Early_ODT
Configure Write_Early_ODT.