ASRock Fatal1ty Z370 Gaming-ITX/ac User Manual - Page 66
Odt Park Ch B, Odt Nom Ch
View all ASRock Fatal1ty Z370 Gaming-ITX/ac manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 66 highlights
RFR Delay (CH B) Configure RFR Delay for Channel B. Advanced Setting ODT WR (CH A) Configure the memory on die termination resistors' WR for channel A. ODT WR (CH B) Configure the memory on die termination resistors' WR for channel B. ODT PARK (CH A) Configure the memory on die termination resistors' PARK for channel A. ODT PARK (CH B) Configure the memory on die termination resistors' PARK for channel B. ODT NOM (CH A) Use this to change ODT (CH A) Auto/Manual settings. The default is [Auto]. ODT NOM (CH B) Use this to change ODT (CH B) Auto/Manual settings. The default is [Auto]. Dll Bandwidth 0 Configure Dll Bandwidth 0 (1067 MHz) to maximize the performance of intergrated memory controller. Dll Bandwidth 1 Configure Dll Bandwidth 1 (1333 MHz) to maximize the performance of intergrated memory controller. Dll Bandwidth 2 Configure Dll Bandwidth 2 (1600 MHz) to maximize the performance of intergrated memory controller. Dll Bandwidth 3 Configure Dll Bandwidth 3 (1867 MHz) to maximize the performance of intergrated memory controller. Command Tristate Enable or disable Command Tristate support. 56 English