ASRock Fatal1ty Z370 Gaming K6 User Manual - Page 77

DRAM Activating Power Supply, CPU Internal PLL Voltage

Get ASRock Fatal1ty Z370 Gaming K6 PDF manuals and user guides View all ASRock Fatal1ty Z370 Gaming K6 manuals
Add to My Manuals
Save this manual to your list of manuals

Page 77 highlights

Fatal1ty Z370 Gaming K6 Series DRAM Voltage Use this to configure DRAM Voltage. The default value is [Auto]. DRAM Activating Power Supply Configure the voltage for the DRAM Activating Power Supply. PCH +1.0 Voltage Configure the chipset voltage (1.0V). VCCIO Voltage Configure the voltage for the VCCIO. VCCST Voltage Configure the voltage for the VCCST. VCCSA Voltage Configure the voltage for the VCCSA. VCCPLL Voltage Configure the voltage for the VCCPLL. CPU Internal PLL Voltage Default is 0.900V. Each step is 0.015V. Adding 9- 15 steps will helps CPU PLL to lock internal clock during High frequency under Ln2 cooling. For example: 1.020V 1.125V will be proper value. But the voltage level will be different on each processor. User has to find the best value for your own processor. CPU Vcore Voltage must higher than CPU Internal PLL Voltage, or your processor will hang. GT PLL Voltage Default is 0.900V. Each step is 0.015V. Adding 9 -15 steps will help CPU PLL to lock internal clock during High frequency under Ln2 cooling. For example: 1.020V 1.125V will be proper value. Bu the voltage level will be different on each processor. User has to find the best value for user's own processor. Ring PLL Voltage Default is 0.900V. Each step is 0.015V. Adding 9 -15 steps will help CPU PLL to lock internal clock during High frequency under Ln2 cooling. For example: 1.020V 1.125V will be proper value. Bu the voltage level will be different on each processor. User has to find the best value for user's own processor. 69 English

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
English
69
Fatal1ty Z370 Gaming K6 Series
DRAM Voltage
Use this to configure DRAM Voltage. °e default value is [Auto].
DRAM Activating Power Supply
Configure the voltage for the DRAM Activating Power Supply.
PCH +1.0 Voltage
Configure the chipset voltage (1.0V).
VCCIO Voltage
Configure the voltage for the VCCIO.
VCCST Voltage
Configure the voltage for the VCCST.
VCCSA Voltage
Configure the voltage for the VCCSA.
VCCPLL Voltage
Configure the voltage for the VCCPLL.
CPU Internal PLL Voltage
Default is 0.900V. Each step is 0.015V. Adding 9- 15 steps will helps CPU PLL to lock
internal clock during High frequency under Ln2 cooling. For example: 1.020V -
1.125V will be proper value. But the voltage level will be different on each processor.
User has to find the best value for your own processor. CPU Vcore Voltage must
higher than CPU Internal PLL Voltage, or your processor will hang.
GT PLL Voltage
Default is 0.900V. Each step is 0.015V. Adding 9 -15 steps will help CPU PLL to lock
internal clock during High frequency under Ln2 cooling. For example: 1.020V -
1.125V will be proper value. Bu the voltage level will be different on each processor.
User has to find the best value for user’s own processor.
Ring PLL Voltage
Default is 0.900V. Each step is 0.015V. Adding 9 -15 steps will help CPU PLL to lock
internal clock during High frequency under Ln2 cooling. For example: 1.020V -
1.125V will be proper value. Bu the voltage level will be different on each processor.
User has to find the best value for user’s own processor.