ASRock H110M-GL/D3 User Manual - Page 41

RAS to RAS Delay tRRD

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H110M-GL/D3 and assign the appropriate frequency automatically. Primary Timing CAS# Latency (tCL) he time between sending a column address to the memory and the beginning of the data in response. RAS# to CAS# Delay and Row Precharge (tRCDtRP) O RAS# to CAS# Delay : he number of clock cycles required between the opening of a row of memory and accessing columns within it. Row Precharge: he number of clock cycles required between the issuing of the precharge command and opening the next row. RAS# Active Time (tRAS) he number of clock cycles required between a bank active command and issuing the precharge command. Command Rate (CR) he delay between when a memory chip is selected and when the irst active command can be issued. Secondary Timing Write Recovery Time (tWR) he amount of delay that must elapse ater the completion of a valid write operation, before an active bank can be precharged. Refresh Cycle Time (tRFC) he number of clocks from a Refresh command until the irst Activate command to the same rank. RAS to RAS Delay (tRRD) he number of clocks between two rows activated in diferent banks of the same rank. Write to Read Delay (tWTR) he number of clocks between the last valid write operation and the next read command to the same internal bank. 37 English

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37
English
H110M-GL/D3
and assign the appropriate frequency automatically.
Primary Timing
CAS# Latency (tCL)
He time between sending a column address to the memory and the beginning of the data
in response.
RAS# to CAS# Delay and Row Precharge (tRCDtRP) O
RAS# to CAS# Delay : He number of clock cycles required between the opening of
a row of memory and accessing columns within it.
Row Precharge: He number of clock cycles required between the issuing of the
precharge command and opening the next row.
RAS# Active Time (tRAS)
He number of clock cycles required between a bank active command and issuing the
precharge command.
Command Rate (CR)
He delay between when a memory chip is selected and when the ±rst active command can
be issued.
Secondary Timing
Write Recovery Time (tWR)
He amount of delay that must elapse aTer the completion of a valid write operation,
before an active bank can be precharged.
Refresh Cycle Time (tRFC)
He number of clocks from a Refresh command until the ±rst Activate command to
the same rank.
RAS to RAS Delay (tRRD)
He number of clocks between two rows activated in diµerent banks of the same
rank.
Write to Read Delay (tWTR)
He number of clocks between the last valid write operation and the next read command to
the same internal bank.