ASRock H310CM-HDVP User Manual - Page 49
RAS# Active Time tRAS, Write Recovery Time tWR
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GT Current Limit Configure the current limit of the GT slice. A lower limit can protect the CPU and save power, while a higher limit may improve performance. DRAM Configuration DRAM Tweaker Fine tune the DRAM settings by leaving marks in checkboxes. Click OK to confirm and apply your new settings. DRAM Timing Configuration DRAM Frequency If [Auto] is selected, the motherboard will detect the memory module(s) inserted and assign the appropriate frequency automatically. Primary Timing CAS# Latency (tCL) The time between sending a column address to the memory and the beginning of the data in response. RAS# to CAS# Delay and Row Precharge (tRCDtRP) RAS# to CAS# Delay : The number of clock cycles required between the opening of a row of memory and accessing columns within it. Row Precharge: The number of clock cycles required between the issuing of the precharge command and opening the next row. RAS# Active Time (tRAS) The number of clock cycles required between a bank active command and issuing the precharge command. Command Rate (CR) The delay between when a memory chip is selected and when the first active command can be issued. Secondary Timing Write Recovery Time (tWR) The amount of delay that must elapse after the completion of a valid write operation, before an active bank can be precharged. 44 English