ASRock H310M-HDV/M.2 User Manual - Page 51

IO-L Offset CH B

Page 51 highlights

tWRWR_dd Configure between module write to write delay. Round Trip Timing RTL Init Value Configure round trip latency init value for round trip latency training. IO-L Init Value Configure IO latency init value for IO latency training. RTL (CH A) Configure round trip latency for channel A. RTL (CH B) Configure round trip latency for channel B. IO-L (CH A) Configure IO latency for channel A. IO-L (CH B) Configure IO latency for channel B. IO-L Offset (CH A) Configure IO latency offset for channel A. IO-L Offset (CH B) Configure IO latency offset for channel B. RFR Delay (CH A) Configure RFR Delay for Channel A. RFR Delay (CH B) Configure RFR Delay for Channel B. ODT Setting ODT WR (A1) Configure the memory on die termination resistors' WR for channel A. ODT WR (B1) Configure the memory on die termination resistors' WR for channel B. 46 English

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English
46
tWRWR_dd
Configure between module write to write delay.
Round Trip Timing
RTL Init Value
Configure round trip latency init value for round trip latency training.
IO-L Init Value
Configure IO latency init value for IO latency training.
RTL (CH A)
Configure round trip latency for channel A.
RTL (CH B)
Configure round trip latency for channel B.
IO-L (CH A)
Configure IO latency for channel A.
IO-L (CH B)
Configure IO latency for channel B.
IO-L Offset (CH A)
Configure IO latency offset for channel A.
IO-L Offset (CH B)
Configure IO latency offset for channel B.
RFR Delay (CH A)
Configure RFR Delay for Channel A.
RFR Delay (CH B)
Configure RFR Delay for Channel B.
ODT Setting
ODT WR (A1)
Configure the memory on die termination resistors' WR for channel A.
ODT WR (B1)
Configure the memory on die termination resistors' WR for channel B.