ASRock H81M-DG4 User Manual - Page 52
CAS# Latency tCL, Row Precharge Time tRP, RAS# Active Time tRAS, Command Rate CR
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DRAM Coniguration CAS# Latency (tCL) he time between sending a column address to the memory and the beginning of the data in response. RAS# to CAS# Delay (tRCD) he number of clock cycles required between the opening of a row of memory and accessing columns within it. Row Precharge Time (tRP) he number of clock cycles required between the issuing of the precharge command and opening the next row. RAS# Active Time (tRAS) he number of clock cycles required between a bank active command and issuing the precharge command. Command Rate (CR) he delay between when a memory chip is selected and when the irst active command can be issued. Write Recovery Time (tWR) he amount of delay that must elapse ater the completion of a valid write operation, before an active bank can be precharged. 48 English