ASRock H81M-ITX/WiFi User Manual - Page 69
Write to Read Delay tWTR, RAS to RAS Delay tRRD
View all ASRock H81M-ITX/WiFi manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 69 highlights
H81M-ITX/WiFi Refresh Cycle Time (tRFC) The number of clocks from a Refresh command until the first Activate command to the same rank. RAS to RAS Delay (tRRD) The number of clocks between two rows activated in different banks of the same rank. Write to Read Delay (tWTR) The number of clocks between the last valid write operation and the next read command to the same internal bank. Read to Precharge (tRTP) The number of clocks that are inserted between a read command to a row precharge command to the same rank. Four Activate Window (tFAW) The time window in which four activates are allowed the same rank. CAS Write Latency (tCWL) Configure CAS Write Latency. tREFI Configure refresh cycles at an average periodic interval. tCKE Configure the period of time the DDR3 initiates a minimum of one refresh command internally once it enters Self-Refresh mode. tRDRD Configure between module read to read delay. tRDRDDR Configure between module read to read delay from different ranks. tRDRDDD Use this to change DRAM tRWSR Auto/Manual settings. The default is [Auto]. tWRRD Configure between module write to read delay. 65 English