ASRock Vision 3D 146B User Manual - Page 41

Active Processor Cores, Intel R SpeedSteptm tech., Intel R TurboMode tech., TDC Limit Override, TDP

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Active Processor Cores Use this item to select the number of cores to enable in each processor package. Configuration options: [All], [1] and [2]. The default value is [All]. A20M Use this item to enable or disable A20M. Legacy OS and AP may need A20M enabled. The default value is [Disabled]. Intel (R) SpeedStep(tm) tech. Intel (R) SpeedStep(tm) tech. is Intel's new power saving technology. Processor can switch between multiple frequency and voltage points to enable power savings. The default value is [Enabled]. Configuration options: [Auto], [Enabled] and [Disabled]. If you install Windows® XP and select [Auto], you need to set the "Power Schemes" as "Portable/Laptop" to enable this function. If you install Windows® VistaTM / 7 and want to enable this function, please set this item to [Enabled]. Please note that enabling this function may reduce CPU voltage and lead to system stability or compatibility issue with some power supplies. Please set this item to [Disable] if above issue occurs. Intel (R) TurboMode tech. Turbo mode allows processor cores to run faster than marked frequency in specific condition. The default value is [Enabled]. TDC Limit Override Program the thresholds for the current while in Turbo mode. The default value is [Disabled]. TDP Limit Override Program the thresholds for the power while in Turbo mode. The default value is [Disabled]. Intel (R) C-STATE tech. Intel (R) C-STATE tech. is achieved by making the power and thermal control unit part of the core logic and not part of the chipset as before. Migration of the power and thermal management flow into the processor allows us to use a hardware coordination mechanism in which each core can request any C-state it wishes, thus allowing for individual core savings to be maximized. The CPU C-state is determined and entered based on the lowest common denominator of both cores' requests, portraying a single CPU entity to the chipset power management hardware and flows. Thus, software can manage each core independently, while the actual power management adheres to the platform and CPU shared resource restrictions. C6 State Use this to select Nehalem C state action. 41

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Please note that enabling this function may reduce CPU voltage and lead to system
stability or compatibility issue with some power supplies. Please set this item to
[Disable] if above issue occurs.
Active Processor Cores
Use this item to select the number of cores to enable in each processor
package. Configuration options: [All], [1] and [2]. The default value is [All].
A20M
Use this item to enable or disable A20M. Legacy OS and AP may need A20M
enabled. The default value is [Disabled].
Intel (R) SpeedStep(tm) tech.
Intel (R) SpeedStep(tm) tech. is Intel’s new power saving technology.
Processor can switch between multiple frequency and voltage points to
enable power savings. The default value is [Enabled]. Configuration options:
[Auto], [Enabled] and [Disabled]. If you install Windows
®
XP and select
[Auto], you need to set the “Power Schemes” as “Portable/Laptop” to en-
able this function.
If you install Windows
®
Vista
TM
/ 7 and want to enable
this function, please set this item to [Enabled].
Intel (R) TurboMode tech.
Turbo mode allows processor cores to run faster than marked frequency
in specific condition. The default value is [Enabled].
TDC Limit Override
Program the thresholds for the current while in Turbo mode. The default
value is [Disabled].
TDP Limit Override
Program the thresholds for the power while in Turbo mode. The default
value is [Disabled].
Intel (R) C-STATE tech.
Intel (R) C-STATE tech. is achieved by making the power and thermal con-
trol unit part of the core logic and not part of the chipset as before. Migration
of the power and thermal management flow into the processor allows us
to use a hardware coordination mechanism in which each core can re-
quest any C-state it wishes, thus allowing for individual core savings to be
maximized. The CPU C-state is determined and entered based on the low-
est common denominator of both cores’ requests, portraying a single CPU
entity to the chipset power management hardware and flows. Thus, soft-
ware can manage each core independently, while the actual power man-
agement adheres to the platform and CPU shared resource restrictions.
C6 State
Use this to select Nehalem C state action.