ASRock X299 Extreme4 User Manual - Page 70
Write to Read Delay tWTR_L
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Write to Read Delay (tWTR) The number of clocks between the last valid write operation and the next read command to the same internal bank. Write to Read Delay (tWTR_L) The number of clocks between the last valid write operation and the next read command to the same internal bank. Read to Precharge (tRTP) The number of clocks that are inserted between a read command to a row precharge command to the same rank. Four Activate Window (tFAW) The time window in which four activates are allowed the same rank. CAS Write Latency (tCWL) Configure CAS Write Latency. Third Timing tREFI Configure refresh cycles at an average periodic interval. tCKE Configure the period of time the DDR4 initiates a minimum of one refresh command internally once it enters Self-Refresh mode. tCCD Configure back to back CAS to CAS (i.e. READ to RAED or WRITE to WRITE) from same rank separation parameter. tCCD_L Configure back to back CAS to CAS (i.e. READ to RAED or WRITE to WRITE) from same rank separation parameter. tCCD_WR_L Configure back to back CAS to CAS (i.e. READ to RAED or WRITE to WRITE) from same rank separation parameter. 64 English