ASRock Z270 Taichi User Manual - Page 68

Minimum CPU Cache Ratio, CPU Slew Rate

Page 68 highlights

Z270 Taichi CPU Cache Ratio The CPU Internal Bus Speed Ratio. The maximum should be the same as the CPU Ratio. Minimum CPU Cache Ratio Set the minimum CPU Internal Bus Speed Ratio. BCLK Frequency The CPU speed is determined by the CPU Ratio multiplied with the BCLK. Increasing the BCLK will increase the internal CPU clock speed but also affect the clock speed of other components. Spread Spectrum Enable Spread Spectrum to reduce electromagnetic interference for passing EMI tests. Disable to achieve higher clock speeds when overclocking. CPU Amplitude Configure the CPU Amplitude. CPU Slew Rate Adjust the BCLK signal by defining the maximum change rate of the output voltage. Higher values will result in a shorter signal rising time. CPU PLL ORT Configure the CPU PLL ORT. Divider The default is set to 4 where the max BCLK is 300 MHz, while divider 12 lowers the max BCLK to 170 MHz, and divider 2 turns it into 300+ MHz. Boot Performance Mode Select the performance state that the BIOS will set before OS handoff. Reliability Stress Restrictor Disable or Enable Reliability Stress Restrictor feature. FCLK Frequency Configure the FCLK Frequency. 61 English

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61
English
Z270 Taichi
CPU Cache Ratio
°e CPU Internal Bus Speed Ratio. °e maximum should be the same as the CPU
Ratio.
Minimum CPU Cache Ratio
Set the minimum CPU Internal Bus Speed Ratio.
BCLK Frequency
°e CPU speed is determined by the CPU Ratio multiplied with the BCLK.
Increasing the BCLK will increase the internal CPU clock speed but also affect the
clock speed of other components.
Spread Spectrum
Enable Spread Spectrum to reduce electromagnetic interference for passing EMI
tests. Disable to achieve higher clock speeds when overclocking.
CPU Amplitude
Configure the CPU Amplitude.
CPU Slew Rate
Adjust the BCLK signal by defining the maximum change rate of the output voltage.
Higher values will result in a shorter signal rising time.
CPU PLL ORT
Configure the CPU PLL ORT.
Divider
°e default is set to 4 where the max BCLK is 300 MHz, while divider 12 lowers the
max BCLK to 170 MHz, and divider 2 turns it into 300+ MHz.
Boot Performance Mode
Select the performance state that the BIOS will set before OS handoff.
Reliability Stress Restrictor
Disable or Enable Reliability Stress Restrictor feature.
FCLK Frequency
Configure the FCLK Frequency.