ASRock Z490 Extreme4 User Manual - Page 73

MRS tCCD_L, ASRock Timing Optimization

Get ASRock Z490 Extreme4 PDF manuals and user guides View all ASRock Z490 Extreme4 manuals
Add to My Manuals
Save this manual to your list of manuals

Page 73 highlights

Z490 Extreme4 Contorl Slew Rate Adjust Control Slew Rate for better signal. Default is 53. Clock Slew Rate Adjust Clock Slew Rate for better signal. Default is 53. Dll Bandwidth 0 Configure Dll Bandwidth 0 (1067 MHz) to maximize the performance of intergrated memory controller. Dll Bandwidth 1 Configure Dll Bandwidth 1 (1333 MHz) to maximize the performance of intergrated memory controller. Dll Bandwidth 2 Configure Dll Bandwidth 2 (1600 MHz) to maximize the performance of intergrated memory controller. Dll Bandwidth 3 Configure Dll Bandwidth 3 (1867 MHz) to maximize the performance of intergrated memory controller. MRS Setting MRS tCL Configure the tCL for Memory MRS MR0. MRS tWRtRTP Configure the tWRtRTP for Memory MRS MRC. MRS tCWL Configure the tCWL for Memory MRS MR2. MRS tCCD_L Configure the tCL for Memory MRS MR6. Advanced Setting ASRock Timing Optimization Configure the fast path through the MRC. 67 English

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
English
67
Z490 Extreme4
Contorl Slew Rate
Adjust Control Slew Rate for better signal. Default is 53.
Clock Slew Rate
Adjust Clock Slew Rate for better signal. Default is 53.
Dll Bandwidth 0
Configure Dll Bandwidth 0 (1067 MHz) to maximize the performance of
intergrated memory controller.
Dll Bandwidth 1
Configure Dll Bandwidth 1 (1333 MHz) to maximize the performance of intergrated
memory controller.
Dll Bandwidth 2
Configure Dll Bandwidth 2 (1600 MHz) to maximize the performance of
intergrated memory controller.
Dll Bandwidth 3
Configure Dll Bandwidth 3 (1867 MHz) to maximize the performance of intergrated
memory controller.
MRS Setting
MRS tCL
Configure the tCL for Memory MRS MR0.
MRS tWRtRTP
Configure the tWRtRTP for Memory MRS MRC.
MRS tCWL
Configure the tCWL for Memory MRS MR2.
MRS tCCD_L
Configure the tCL for Memory MRS MR6.
Advanced Setting
ASRock Timing Optimization
Configure the fast path through the MRC.