ASRock Z690 Taichi User Manual - Page 93

Initial RTL MC1 C1 B1/B2

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Initial RTL (MC0 C0 A1/A2) Configure round trip latency initial value. Initial RTL (MC0 C1 A1/A2) Configure round trip latency initial value. Initial RTL (MC1 C0 B1/B2) Configure round trip latency initial value. Initial RTL (MC1 C1 B1/B2) Configure round trip latency initial value. RTL (MC0 C0 A1/A2) Configure round trip latency value. RTL (MC0 C1 A1/A2) Configure round trip latency value. RTL (MC1 C0 B1/B2) Configure round trip latency value. RTL (MC1 C1 B1/B2) Configure round trip latency value. ODT Setting Dimm ODT Training ODT values will be optimized by Dimm On-Die Termination Training. ODT WR (A1) Configure the memory on die termination resistors' WR for channel A1. ODT WR (A2) Configure the memory on die termination resistors' WR for channel A2. ODT WR (B1) Configure the memory on die termination resistors' WR for channel B1. ODT WR (B2) Configure the memory on die termination resistors' WR for channel B2. Z690 Taichi 85 English

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English
85
Z690 Taichi
Initial RTL (MC0 C0 A1/A2)
Configure round trip latency initial value.
Initial RTL (MC0 C1 A1/A2)
Configure round trip latency initial value.
Initial RTL (MC1 C0 B1/B2)
Configure round trip latency initial value.
Initial RTL (MC1 C1 B1/B2)
Configure round trip latency initial value.
RTL (MC0 C0 A1/A2)
Configure round trip latency value.
RTL (MC0 C1 A1/A2)
Configure round trip latency value.
RTL (MC1 C0 B1/B2)
Configure round trip latency value.
RTL (MC1 C1 B1/B2)
Configure round trip latency value.
ODT Setting
Dimm ODT Training
ODT values will be optimized by Dimm On-Die Termination Training.
ODT WR (A1)
Configure the memory on die termination resistors' WR for channel A1.
ODT WR (A2)
Configure the memory on die termination resistors' WR for channel A2.
ODT WR (B1)
Configure the memory on die termination resistors' WR for channel B1.
ODT WR (B2)
Configure the memory on die termination resistors' WR for channel B2.