ASRock Z87iCafe4 User Manual - Page 56

RAS to RAS Delay tRRD, Write to Read Delay tWTR

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DRAM Tweaker Fine tune the DRAM settings by leaving marks in checkboxes. Click OK to confirm and apply your new settings. CAS# Latency (tCL) The time between sending a column address to the memory and the beginning of the data in response. RAS# to CAS# Delay (tRCD) The number of clock cycles required between the opening of a row of memory and accessing columns within it. Row Precharge Time (tRP) The number of clock cycles required between the issuing of the precharge command and opening the next row. RAS# Active Time (tRAS) The number of clock cycles required between a bank active command and issuing the precharge command. Command Rate (CR) The delay between when a memory chip is selected and when the first active command can be issued. Write Recovery Time (tWR) The amount of delay that must elapse after the completion of a valid write operation, before an active bank can be precharged. Refresh Cycle Time (tRFC) The number of clocks from a Refresh command until the first Activate command to the same rank. RAS to RAS Delay (tRRD) The number of clocks between two rows activated in different banks of the same rank. Write to Read Delay (tWTR) The number of clocks between the last valid write operation and the next read command to the same internal bank. 52 English

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52
English
DRAM Tweaker
Fine tune the DRAM settings by leaving marks in checkboxes. Click OK to confirm and
apply your new settings.
CAS# Latency (tCL)
°e time between sending a column address to the memory and the beginning of the data
in response.
RAS# to CAS# Delay (tRCD)
°e number of clock cycles required between the opening of a row of memory and
accessing columns within it.
Row Precharge Time (tRP)
°e number of clock cycles required between the issuing of the precharge command
and opening the next row.
RAS# Active Time (tRAS)
°e number of clock cycles required between a bank active command and issuing the
precharge command.
Command Rate (CR)
°e delay between when a memory chip is selected and when the first active command can
be issued.
Write Recovery Time (tWR)
°e amount of delay that must elapse aſter the completion of a valid write operation,
before an active bank can be precharged.
Refresh Cycle Time (tRFC)
°e number of clocks from a Refresh command until the first Activate command to
the same rank.
RAS to RAS Delay (tRRD)
°e number of clocks between two rows activated in different banks of the same
rank.
Write to Read Delay (tWTR)
°e number of clocks between the last valid write operation and the next read
command to the same internal bank.