ASRock Z97 Anniversary User Manual - Page 71

tRDRD, tWRRD, RTL CHA, Configure between module write to write delay from different DIMMs.

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tRDRD Configure between module read to read delay. tRDRDDR Configure between module read to read delay from different ranks. tRDRDDD Use this to change DRAM tRWSR Auto/Manual settings. The default is [Auto]. tWRRD Configure between module write to read delay. tWRRDDR Configure between module write to read delay from different ranks. tWRRDDD Use this to change DRAM tRRSR Auto/Manual settings. The default is [Auto]. Configure between module write to read delay from different DIMMs. tWRWR Configure between module write to write delay. tWRWRDR Configure between module write to write delay from different ranks. tWRWRDD Configure between module write to write delay from different DIMMs. tRDWR Configure between module read to write delay. tRDWRDR Configure between module read to write delay from different ranks. tRDWRDD Configure between module read to write delay from different DIMMs. RTL (CHA) Configure round trip latency for channel A. 66 English

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66
English
tRDRD
Configure between module read to read delay.
tRDRDDR
Configure between module read to read delay from different ranks.
tRDRDDD
Use this to change DRAM tRWSR Auto/Manual settings. °e default is [Auto].
tWRRD
Configure between module write to read delay.
tWRRDDR
Configure between module write to read delay from different ranks.
tWRRDDD
Use this to change DRAM tRRSR Auto/Manual settings. °e default is [Auto].
Configure between module write to read delay from different DIMMs.
tWRWR
Configure between module write to write delay.
tWRWRDR
Configure between module write to write delay from different ranks.
tWRWRDD
Configure between module write to write delay from different DIMMs.
tRDWR
Configure between module read to write delay.
tRDWRDR
Configure between module read to write delay from different ranks.
tRDWRDD
Configure between module read to write delay from different DIMMs.
RTL (CHA)
Configure round trip latency for channel A.