Acer Aspire 5538 Acer Aspire 5538 Series Service Guide - Page 181

DLL Timing Control Registers, RCOMP settings Post Code 0x27 0x28 0x29 0x30 0x31 0x32 0x33 0x34 0x35 0x43 Description Enable DRAM Channel I/O Buffers Enable all clocks on populated rows Perform JEDEC memory initialization for all memory rows Perform steps required after memory init Program DRAM throttling and throttling event registers Setup DRAM control register for normal operation and enable Enable RCOMP Clear DRAM initialization bit in the SB Initialization Sequence Completed, program graphic clocks Program Thermal Throttling 171 Chapter 4