Acer Aspire 8951G Acer Aspire 8951G Notebook Service Guide - Page 174

Post Codes 0 The following are the InsydeH2O™ Functionality POST code tables. The components of the POST code table includes: SEC phase, PEI phase, DXE phase, BDS phase, CSM functions, S3 functions and ACPI functions. SEC PEI DXE BDS SMM S3 ASL Phase PostBDS InsydeH2ODDT™ Reserve OEM Reserve Reserved POST Code Range 0x01 - 0x0F 0x70 - 0x9F 0x40 - 0x6F 0x10 - 0x3F 0xA0 - 0xBF 0xC0 - 0xCF 0x51 - 0x55 0xE1 - 0xE4 0xF9 - 0xFE 0xD0 - 0xD7 0xE8 - 0xEB 0xD8 - 0xE0 0xE5 - 0xE7 0xEC - 0xF8 Functionality Name (Include\PostCode.h) SEC_SYSTEM_POWER_ON SEC_BEFORE_MICROCODE_PATCH SEC_AFTER_MICROCODE_PATCH SEC_ACCESS_CSR* SEC_GENERIC_MSRINIT* SEC_CPU_SPEEDCFG* SEC_SETUP_CAR_OK SEC_FORCE_MAX_RATIO* SEC_GO_TO_SECSTARTUP Phase Post Code Description SEC 01 CPU power on and switch to Protected mode SEC 02 Patching CPU microcode SEC 03 Setup Cache as RAM SEC 04 PCIE MMIO Base Address initial SEC 05 CPU Generic MSR initialization SEC 06 Setup CPU speed SEC 07 Cache as RAM test SEC 08 Tune CPU frequency ratio to maximum level SEC 09 Setup BIOS ROM cache 4-22 Troubleshooting