Acer Aspire M3-581T Acer Aspire M3-581T and M3-581TG Notebook Service Guide - Page 186

Post Codes, POST Code Range

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Post Codes 0 The following are the InsydeH2O™ Functionality POST code tables. The components of the POST code table includes: SEC phase, PEI phase, DXE phase, BDS phase, CSM functions, S3 functions and ACPI functions. POST Code Range 0 Table 4-2. POST Code Range SEC PEI DXE BDS SMM S3 ASL Phase PostBDS InsydeH2ODDT™ Reserve OEM Reserve Reserved POST Code Range 0x01 - 0x0F 0x70 - 0x9F 0x40 - 0x6F 0x10 - 0x3F 0xA0 - 0xBF 0xC0 - 0xCF 0x51 - 0x55 0xE1 - 0xE4 0xF9 - 0xFE 0xD0 - 0xD7 0xE8 - 0xEB 0xD8 - 0xE0 0xE5 - 0xE7 0xEC - 0xF8 Table 4-3. SEC Phase POST Code Table Functionality Name (Include\ PostCode.h) SEC_SYSTEM_POWER_ON SEC_BEFORE_MICROCODE_PATCH Phase SEC SEC Post Code 1 2 Description CPU power on and switch to Protected mode Patching CPU microcode SEC_AFTER_MICROCODE_PATCH SEC_ACCESS_CSR* SEC_GENERIC_MSRINIT* SEC_CPU_SPEEDCFG* SEC 3 SEC 4 SEC 5 SEC 6 Setup Cache as RAM PCIE MMIO Base Address initial CPU Generic MSR initialization Setup CPU speed 4-20 Troubleshooting

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