Acer Aspire M3100 Aspire M1100/3100/5100 Power M3100 Service Guide - Page 29
South Bridge, Wake-up Event Specification (Default Setting in BIOS) - chipset
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South Bridge Item Chipset Feature Specification ATI SB600 A-Link Express II interface to the RADEON IGPs: • 1/2/4-lane A-link Express II interface • Dynamic detection of lane configuration PCI Host Bus Controller: • Support PCI Rev. 2.3 specification • Support PCI Bus at 33MHz • Support up to 6 bus master device • Support 40-bit addressing USB Controller: • 5 OHCI and 1 EHCI Host controller to support 10 USB ports • All10 ports are USB 1.1("Low speed", "Full speed") and 2.0("High speed") compatible • Support ACPI S1~S5 SMBus Controller: • SMBus Rev. 2.0 compliant • Support SMBALERT# signal/GPIO DMA Controller: • 2 cascaded 8237 DMA controllers • Support PC/PCI DMA • Support LPC DMA • Support type F DMA Wake-up Event Specification (Default Setting in BIOS) Power button PS2 keyboard USB keyboard PME Modem (ring) RTC S1 Enable (default), Disabled Enabled, Disabled (default) Enabled (default), Disabled Enabled (default), Disabled Enabled, Disabled (default) Enabled, Disabled (default) S3 Enabled (default), Disabled Enabled, Disabled (default) Enabled (default), Disabled Enabled (default), Disabled Enabled, Disabled (default) Enabled, Disabled (default) S4 Enabled (default), Disabled N/A Enabled (default) Disabled Enabled (default), Disabled Enabled, Disabled (default) Enabled, Disabled (default) S5 Enabled (default), Disabled N/A N/A Enabled (default), Disabled Enabled, Disabled (default) Enabled, Disabled (default) Chapter 1 19