Asus AS-D692 AS-D692 User's Manual for Traditional Chinese Edition - Page 81

CPU Configuration

Page 81 highlights

5.4.3 CPU Configuration Configure Advanced CPU settings Manufacturer: Intel Brand String: Genuine Intel(R) CPU 3.20GHz Frequency : 3200 MHz FSB Speed : 800 MHz Cache L1 Cache L2 Cache L3 : 16 KB : 1024 KB : 0 KB Microcode Updation: Max CPUID Value Limit: Enhanced C1 Control CPU Internal Thermal Control Hyper Threading Technology Intel(R) SpeedStep(tm) Tech. [Enabled] [Disabled] [Auto] [Auto] [Enabled] [Automatic] Sets the ratio between CPU Core Clock and the FSB Frequency. NOTE: If an invalid ratio is set in CMOS then actual and setpoint values may differ. Select Screen Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit Microcode Updation [Enabled] Microcode Updation [Disabled] [Enabled] Max CPUID Value Limit [Disabled] [Enabled] CPUID [Disabled] [Enabled] Execute Disabled Function [Disabled] [Disabled] [Enabled] Enhanced C1 Control [Auto] [Auto] BIOS C1E C1E [Auto] [Disabled] CPU Internal Thermal Control [Auto] [Auto] [Disabled] 5-25

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5-25
5.4.3
CPU Configuration
Microcode Updation [Enabled]
Microcode Updation
[Disabled] [Enabled]
Max CPUID Value Limit [Disabled]
CPUID
[Enabled]
[Disabled] [Enabled]
Execute Disabled Function [Disabled]
[Disabled] [Enabled]
Enhanced C1 Control [Auto]
[Auto]
BIOS
C1E
C1E
[Auto] [Disabled]
CPU Internal Thermal Control [Auto]
[Auto] [Disabled]
Select Screen
Select Item
+-
Change Option
F1
General Help
F10
Save and Exit
ESC
Exit
Configure Advanced CPU settings
Manufacturer: Intel
Brand String: Genuine Intel(R) CPU 3.20GHz
Frequency
: 3200 MHz
FSB Speed
: 800 MHz
Cache L1
: 16 KB
Cache L2
: 1024 KB
Cache L3
: 0 KB
Microcode Updation:
[Enabled]
Max CPUID Value Limit:
[Disabled]
Enhanced C1 Control
[Auto]
CPU Internal Thermal Control
[Auto]
Hyper Threading Technology
[Enabled]
Intel(R) SpeedStep(tm) Tech.
[Automatic]
Sets the ratio between
CPU Core Clock and the
FSB Frequency.
NOTE: If an invalid
ratio is set in CMOS
then actual and
setpoint values may
differ.