Asus M3N78-EM User Guide - Page 76
Chipset, Chipset
UPC - 610839164417
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2.4.3 Chipset Chipset Configuration NorthBridge Configuration Internal Graphics Memory Options & Information NorthBridge Configuration NorthBridge Chipset Configuration Memory Configuration ECC Configuration Memory CLK CAS Latency(Tc1) RAS/CAS Delay(Trcd) Row Precharge Time(Trp) Min Active RAS(Tras) RAS/RAS Delay(Trrd) Row Cycle(Trc) :333MHz :5.0 :5 CLK :5 CLK :15 CLK :3 CLK :21 CLK Memory Configuration Advanced Memory Configuration Bank Interleaving Channel Interleaving MemClk Tristate C3/ATLVID Memory Hole Remapping DCT Unganged Mode Power Down Enable [Auto] [Disabled] [Disabled] [Enabled] [Auto] [Enabled] Enable Bank Memory Interleaving Bank Interleaving [Auto] Allows you to enable the bank memory interleaving. Configuration options: [Disabled] [Auto] Channel Interleaving [Disabled] Allows you to enable the channel memory interleaving. Configuration options: [Disabled] [Address bits 6] [Address bits 12] [XOR of Address bits [20:16, 6]] [XOR of Address bits [20:16, 9]] 2-24 Chapter 2: BIOS setup