Asus ROG STRIX X670E-A GAMING WIFI ROG STRIX X670E Series BIOS Manual English - Page 51

UMC Common Options, DDR Options

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UMC Common Options DDR Options DDR Timing Configuration This item allows you to configure DRAM timing configuration. Damage caused by use of your AMD processor outside of specification or in excess of factory settings are not covered by your system manufacturers warranty. The following items appear only when [Accept] is selected for DRAM Timing Configuration. Active Memory Timing Settings Configuration options: [Auto] [Enabled] Memory Target Speed Specifies the memory target speed in MT/s. The valid input is 2000 MT/s, 2400 MT/s, and range of 3200 MT/s ~ 12000 MT/s (stepping of 200 MT/s). The value is in decimal. The user input value will be rounded down to align with the stepping of 200 MT/s. The maximum speed defined in the JEDEC spec is 8400 MT/s, any input value that is greater than 8400 MT/s will be limited to 8400 MT/s. DDR SPD Timing Tcl Ctrl [Auto] [Manual] Follow default setting. Manually specify. The following item appears only when Tcl Ctrl is set to [Manual]. Tcl Specifies the CAS Latency. Valid values: 0x16 ~ 0x40, with a stepping of 2. The value is in hex. Trcd Ctrl [Auto] [Manual] Follow default setting. Manually specify. The following item appears only when Trcd Ctrl is set to [Manual]. Trcd Specifies the RAS# Active to CAS# Read Delay Time. Valid values: 0x8 ~ 0x3E. The value is in hex. Trp Ctrl [Auto] [Manual] Follow default setting. Manually specify. The following item appears only when Trp Ctrl is set to [Manual]. Trp Specifies Row Precharge Delay Time. Valid values: 0x8 ~ 0x3E. The value is in hex. ROG STRIX X670E Series BIOS Manual 51

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ROG STRIX X670E Series BIOS Manual
51
UMC Common Options
DDR Options
DDR Timing Configuration
This item allows you to configure DRAM timing configuration.
Damage caused by use of your AMD processor outside of specification or in excess of
factory settings are not covered by your system manufacturers warranty.
The following items appear only when
[Accept]
is selected for
DRAM Timing
Configuration
.
Active Memory Timing Settings
Configuration options: [Auto] [Enabled]
Memory Target Speed
Specifies the memory target speed in MT/s. The valid input is 2000 MT/s, 2400
MT/s, and range of 3200 MT/s ~ 12000 MT/s (stepping of 200 MT/s). The
value is in decimal. The user input value will be rounded down to align with
the stepping of 200 MT/s. The maximum speed defined in the JEDEC spec
is 8400 MT/s, any input value that is greater than 8400 MT/s will be limited to
8400 MT/s.
DDR SPD Timing
Tcl Ctrl
[Auto]
Follow default setting.
[Manual]
Manually specify.
The following item appears only when
Tcl Ctrl
is set to
[Manual]
.
Tcl
Specifies the CAS Latency. Valid values: 0x16 ~ 0x40, with a stepping
of 2. The value is in hex.
Trcd Ctrl
[Auto]
Follow default setting.
[Manual]
Manually specify.
The following item appears only when
Trcd Ctrl
is set to
[Manual]
.
Trcd
Specifies the RAS# Active to CAS# Read Delay Time. Valid values:
0x8 ~ 0x3E. The value is in hex.
Trp Ctrl
[Auto]
Follow default setting.
[Manual]
Manually specify.
The following item appears only when
Trp Ctrl
is set to
[Manual]
.
Trp
Specifies Row Precharge Delay Time. Valid values: 0x8 ~ 0x3E. The
value is in hex.