Asus TUF GAMING Z490-PLUS Intel 400 series Channel BIOS UM English - Page 19
DRAM WRITE to READ Delay L, DRAM READ to PRE Time
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Primary Timings DRAM CAS# Latency Configuration options: [Auto] [1] - [31] DRAM RAS# to CAS# Delay Configuration options: [Auto] [1] - [63] DRAM RAS# ACT Time Configuration options: [Auto] [1] - [63] DRAM Command Rate Configuration options: [Auto] [1N] [2N] [3N] [N:1] The following item appears only when DRAM Command Rate is set to [N:1]. N to 1 ratio Number of bubbles between wach valid command cycle. Configurations: [4] - [7] Secondary Timings DRAM RAS# to RAS# Delay L Configuration options: [Auto] [1] - [15] DRAM RAS# to RAS# Delay S Configuration options: [Auto] [1] - [15] DRAM REF Cycle Time Configuration options: [Auto] [1] - [1023] DRAM REF Cycle Time 2 Configuration options: [Auto] [1] - [1023] DRAM REF Cycle Time 4 Configuration options: [Auto] [1] - [1023] DRAM Refresh Interval Configuration options: [Auto] [1] - [65535] DRAM WRITE Recovery Time Configuration options: [Auto] [1] - [31] DRAM READ to PRE Time Configuration options: [Auto] [1] - [15] DRAM FOUR ACT WIN Time Configuration options: [Auto] [1] - [63] DRAM WRITE to READ Delay Configuration options: [Auto] [1] - [15] DRAM WRITE to READ Delay L Configuration options: [Auto] [1] - [15] PRIME/PRO/ProArt/TUF GAMING Intel 400 Series BIOS Manual 19