Biostar M7VIQ M7VIQ BIOS setup guide - Page 15

CPU & PCI Bus Control

Page 15 highlights

M7VIQ BIOS Setup The Choices: Auto (default), Manual. AGP Driving Value While AGP driving control item set to "Manual", it allows user to set AGP driving. The Choices: DA (default). AGP Fast Write The Choices: Enabled, Disabled (default). AGP Master 1 WS Write When Enabled, writes to the AGP (Accelerated Graphics Port) are executed with one-wait states. The Choices: Disabled (default), Enabled. AGP Master 1 WS Read When Enabled, read to the AGP (Accelerated Graphics Port) are executed with one wait states. The Choices: Disabled (default), Enabled. CPU & PCI Bus Control If you highlight the literal "Press Enter" next to the "CPU & PCI Bus Control" label and then press the enter key, it will take you a submenu with the following options: PCI1 Master 0 WS Write When enabled, writes to the PCI bus are executed with zero-wait states. The Choices: Enabled (default), Disabled. PCI2 Master 0 WS Write When enabled, writes to the AGP bus are executed with zero-wait states. The Choices: Enabled (default), Disabled. PCI1 Post Write When Enabled, CPU writes are allowed to post on the PCI bus. The Choices: Enabled (default), Disabled. PCI2 Post Write When Enabled, CPU writes are allowed to post on the AGP bus. The Choices: Enabled (default), Disabled. PCI Delay Transaction The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles. Select Enabled to support compliance with PCI specification. The Choices: Enabled (default), Disabled. 14

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M7VIQ BIOS Setup
14
The Choices: Auto
(default), Manual.
AGP Driving Value
While AGP driving control item set to “Manual”, it allows user to set AGP
driving.
The Choices: DA
(default).
AGP Fast Write
The Choices:
Enabled,
Disabled
(default).
AGP Master 1 WS Write
When Enabled, writes to the AGP (Accelerated Graphics Port) are executed with
one-wait states.
The Choices: Disabled
(default), Enabled.
AGP Master 1 WS Read
When Enabled, read to the AGP (Accelerated Graphics Port) are executed with
one wait states.
The Choices: Disabled
(default), Enabled.
CPU & PCI Bus Control
If you highlight the literal “Press Enter” next to the “CPU & PCI Bus Control” label and
then press the enter key, it will take you a submenu with the following options:
PCI1 Master 0 WS Write
When enabled, writes to the PCI bus are executed with zero-wait states.
The Choices: Enabled
(default), Disabled.
PCI2 Master 0 WS Write
When enabled, writes to the AGP bus are executed with zero-wait states.
The Choices: Enabled
(default), Disabled.
PCI1 Post Write
When Enabled, CPU writes are allowed to post on the PCI bus.
The Choices: Enabled
(default), Disabled.
PCI2 Post Write
When Enabled, CPU writes are allowed to post on the AGP bus.
The Choices: Enabled
(default), Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI specification.
The Choices: Enabled
(default), Disabled.