Biostar N68S3 Bios Manual - Page 25

Chipset Menu

Page 25 highlights

MCP6P3/N68S3 BIOS Manual 5 Chipset Menu T his submenu allows you to configure the speci fic features of the chipset installed on your system. T his chipset manage bus speeds and access to system memory resources, such as DRAM. It also coordinates communications with the PCI bus. Main Advanced BIOS S ETUP UTILITY PCIPnP Boot Chips et Perfo rmance Exit Advan ced Chipset S ettings WARNI NG: Setting w rong values in below sec tions ma y cause syst em to malfun ction. > Nor thBridge Conf iguration > Sou thBridge MCP6 1 Configurat ion > Hyp er Transport Configuratio n Opti ons for NB S elect Screen S elect Item En terG o to Sub Scr een F1 G eneral Help F1 0 S ave and Exit ES C E xit vxx.xx (C)C opyright 198 5-200x, Amer ican Megatre nds, Inc. NorthBridge Configuration BIOS S ETUP UTILITY Chips et North Bridge Chipse t Configurat ion > Mem ory Configura tion Alter nate VID [ Auto] Mem ory CLK : CAS Latency(Tcl) : RAS /CAS Delay(Tr cd) : Row Precharge Ti me(Trp): Min Active RAS(T ras) : RAS /RAS Delay(Tr rd) : Row Cycle (Trc) : Wri te Recover Ti me(Twr): S elect Screen S elect Item +- C hange Option F1 G eneral Help F1 0 S ave and Exit ES C E xit vxx.xx (C)C opyright 198 5-200x, Amer ican Megatre nds, Inc. 24

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37

MCP6P3/N68S3 BIOS Manual
24
5 Chipset Menu
This submenu allows you to configure the specific features of the chipset installed on
your system. This chipset manage bus speeds and access to system memory
resources, such as DRAM. It also coordinates communications with the PCI bus.
BIOS SETUP UTILITY
Main
Advanced
PCIPnP
Boot
Chipset
Performance
vxx.xx (C)Copyright 1985-200x, American Megatrends, Inc.
Select Screen
Select Item
Go to Sub Screen
General Help
Save and Exit
Exit
Enter
F1
F10
ESC
Options for NB
Advanced Chipset Settings
WARNING: Setting wrong values in below sections
may cause system to malfunction.
> SouthBridge MCP61 Configuration
> Hyper Transport Configuration
> NorthBridge Configuration
Exit
NorthBridge Configuration
BIOS SETUP UTILITY
vxx.xx (C)Copyright 1985-200x, American Megatrends, Inc.
Select Screen
Select Item
Change Option
General Help
Save and Exit
Exit
+-
F1
F10
ESC
NorthBridge Chipset Configuration
> Memory Configuration
Alternate VID
[Auto]
Memory CLK
:
CAS Latency(Tcl)
:
RAS/CAS Delay(Trcd)
:
Row Precharge Time(Trp):
Min Active RAS(Tras)
:
RAS/RAS Delay(Trrd)
:
Row Cycle (Trc)
:
Write Recover Time(Twr):
Chipset