Dell PowerEdge M610x Technical Guide - Page 25
Overview, I/O Hub
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Dell 8 Chipset 8.1 Overview The Dell™ PowerEdge™ M610x system board incorporates the Intel 5500 chipset for I/O and processor interfacing which was designed to support Intel Xeon Processor 5500 and 5600 Series, QuickPath Interconnect, DDR3 memory technology, and PCI Express Generation 2. The chipset consists of the I/O Hub (IOH) and Intel I/O Controller Hub 9 (ICH9). 8.2 I/O Hub The M610x system board uses the Intel 5520 chipset 24D I/O hub (IOH) to provide a link between the processor(s) and I/O components. The main components of the IOH consist of two full-width QuickPath Interconnect links (one to each processor), 24 lanes of PCI Express Gen2, a x4 Direct Media Interface (DMI), and an integrated IOxAPIC. 8.2.1 QuickPath Interconnect The QuickPath Interconnect (QPI) architecture consists of serial point-to-point interconnects for the processors and the IOH. The M610x has a total of three QPI links: one link connecting the processors and two links connecting both processors with the IOH. Each link consists of 20 lanes (full-width) in each direction with a link speed of 6.4 GT/s. An additional lane is reserved for a forwarded clock. Data is sent over the QPI links as packets. The QuickPath architecture implemented in the IOH and CPUs features four layers. The Physical layer consists of the actual connection between components. It supports Polarity Inversion and Lane Reversal for optimizing component placement and routing. The Link layer is responsible for flow control and the reliable transmission of data. The Routing layer is responsible for the routing of QPI data packets. Finally, the Protocol layer is responsible for high-level protocol communications, including the implementation of a MESIF (Modify, Exclusive, Shared, Invalid, Forward) cache coherence protocol. 8.2.2 PCI Express PCI Express (PCIe) is a serial point-to-point interconnect for I/O devices. PCIe Generation 2 doubles the signaling bit rate of Generation 1 from 2.5 Gb/s to 5 Gb/s. Each of the PCIe Gen2 ports are backward-compatible with Gen1 transfer rates. The IOH 24D has 24 PCI Express lanes. The lanes are partitioned as two x2 ports and combined as a x4 PCI Express Gen2 port for the LOM1. The next port is a x4 PCI Express Gen2 port for LOM2 and the remaining x4 ports are combined as two x8 PCI Express Gen2 ports for the mezzanine cards. These last two x8 Gen2 ports are the entities that provide communication for the M610x functionality. 8.2.3 Direct Media Interface The Direct Media Interface (DMI) connects the IOH with the Intel I/O Controller Hub 9 (ICH9). The DMI is equivalent to a x4 PCIe Gen1 link with a transfer rate of 1 GB/s in each direction. 8.2.4 I/O Controller Hub 9 The I/O Controller Hub 9 (ICH9) is a highly integrated I/O controller, supporting the following functions: Six x1 PCI Express Gen1 ports, with the capability of combining ports 1-4 as a x4 link (The x4 link is routed to the storage controller card connector.) Dell PowerEdge M610x Technical Guide 25