Dell PowerEdge R530 Dell PowerEdge R530 Owners Manual - Page 3

Item Planer PCH Internal CMOS RAM BIOS SPI Flash iDRAC SPI Flash BMC EMMC How is data input to this memory? How is this memory write protected? BIOS SPI interface via iDRAC SPI interface via iDRAC NAND Flash interface via iDRAC N/A - BIOS only control Software write protected Embedded iDRAC subsystem firmware actively controls sub area based write protection as needed. Embedded FW write protected CPU Vcore and VSA Regulators System CPLD RAM System Memory System Memory Power Supplies PSU FW 2U 8x3.5" Backplane SEP internal flash Once values are loaded into register space a cmd writes to nvm. Not utilized There are passwords for different sections of the register space Not accessible System OS RAM System OS System OS OS Control Different vendors have different utilities and tools to load the data to memory. It can also be loaded by Dell Update Package from LC or OS (Windows and Linux) Protected by the embedded microcontroller. Special keys are used by special vendor provided utilities to unlock the ROM with various CRC checks during load. Firmware + FRU I2C interface via iDRAC NOTE: For any information that you may need, direct your questions to your Dell Marketing contact. 2014 Dell Inc. Trademarks used in this text: Dell™, the DELL logo, and PowerEdge™ are trademarks of Dell Inc. Dell - Internal Use - Confidential