Foxconn A7VML English Manual. - Page 38

DRAM Timing Configuration CMOS Setup Utility - Copyright (C) 1985-2008, American Megatrends, Inc. DRAM Timing Configuration DRAM Timing Configuration Help Item DRAM Timing Mode [Auto] Options Auto DCT 0 DCT 1 Both 3 Move Enter:Select +/-/:Value F10:Save ESC:Exit F1:General Help F9:Optimized Defaults ► DRAM Timing Mode When both DCTs (DRAM controller) are enabled in unganged mode, BIOS must initialize the frequency of each DCT in order, you also can configure the timings manually. Settings are: [Auto], [DCT 0], [DCT 1], [Both]. [DCT 1] and [Both] will appear only in AM2+ CPU. ► CAS Latency The number of memory clocks it takes a DRAM to return data after the read CAS_L is asserted depends on the memory clock frequency. The value that BIOS programs into the memory controller is a function of the target clock frequency. The target clock frequency is determined from the supported CAS latencies at given clock frequencies of each DIMM. ► TRCD (RAS-to-CAS Delay) This item allows you to select a delay time (in clock cycles) between the CAS# and RAS# strobe signals. ► TRP (Precharge Command Period) This item allows you to select the row precharge time (in clock cycles). ► tRTP (Internal Read to Precharge Command Delay) Internal READ Command to PRECHARGE Command delay. ► TRAS (Active-to-Precharge Delay) This item allows you to set the minimum RAS# active time (in clock cycles). ► TRC (Active-to-Active/Auto-Refresh Command Period) This item allows you to set the row cycle time (in clock cycles). tRC = tRAS + tRP. ► tWR (Write Recovery) This item allows you to select the write recovery time (in clock cycles). ► TRRD (Active-to-Active of a Different Bank) This item allows you to select a delay time (in clock cycles) between the RAS# and RAS# strobe signals. ► tWTR (Internal Write to Read Command Delay) 31