Foxconn M61PMP-K User manual - Page 35

DRAM Timing Configuration

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3 (64-bit DRAM data width) DRAM modes : Ganged channels (DDR3) : ■ DCT channels A and B can be ganged as a single logical 128-bit DIMM. ■ Offers highest DDR3 bandwidth. ■ Requires both DIMMs in a logical pair to have identical size and timing parameters, both DCTs programmed identically. Unganged channels ■ DCT channels A and B operate as two completely independent 64-bit channels (both chan- nels operate at the same frequency). ■ Reduce DRAM page conflicts - more concurrent open dram pages . ■ Better bus efficiency. Burst lengths supported When both DCTs are enabled in unganged mode, BIOS must initialize the frequency of each DCT in order. DRAM Timing Configuration CMOS Setup Utility - Copyright (C) 1985-2006, American Megatrends, Inc. DRAM Timing Configuration DRAM Timing Configuration Help Item Memory Clock Mode [Auto] Options DRAM Timing Mode [Auto] Auto Limit Manual Move Enter:Select +/-/:Value F10:Save ESC:Exit F1:General Help F9:Optimized Defaults ► Memory Clock Mode This option is used to configuration Memory Frequency, Timings and Subtimings. Setting values are :[Auto],[Limit],[Manual]. [Auto]: DRAM SPD profile1; [Limit]: DRAM SPD profile2; [Manual]: DRAM by Manual. ► DRAM Timing Mode When both DCTs (DRAM controller) are enabled in unganged mode, BIOS must initialize the frequency of each DCT in order, you also can configure the timings manually. Settings are: [Auto], [DCT0], [DCT1], [Both]. 28

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3
28
(64-bit DRAM data width) DRAM modes :
Ganged channels (DDR3) :
■
DCT channels A and B can be ganged as a single logical 128-bit DIMM.
■
Offers highest DDR3 bandwidth.
■
Requires both DIMMs in a logical pair to have identical size and timing parameters, both
DCTs programmed identically.
Unganged channels
■
DCT channels A and B operate as two completely independent 64-bit channels (both chan
-
nels operate at the same frequency).
■
Reduce DRAM page conflicts – more concurrent open dram pages .
■ Better bus efficiency.
Burst lengths supported
When both DCTs are enabled in unganged mode, BIOS must initialize the frequency of each
DCT in order.
DRAM Timing Configuration
CMOS Setup Utility - Copyright (C) 1985-2006, American Megatrends, Inc.
DRAM Timing Configuration
DRAM Timing Configuration
Help Item
Memory Clock Mode
DRAM Timing Mode
[Auto]
Auto
Limit
Manual
↑↓←→:Move
Enter:Select
+/-/:Value
F10:Save
ESC:Exit
F1:General Help
F9:Optimized Defaults
[Auto]
Options
► Memory Clock Mode
This option is used to configuration Memory Frequency, Timings and Subtimings. Setting
values are :[Auto],[Limit],[Manual].
[Auto]: DRAM SPD profile1;
[Limit]: DRAM SPD profile2;
[Manual]: DRAM by Manual.
► DRAM Timing Mode
When both DCTs (DRAM controller) are enabled in unganged mode, BIOS must initialize the
frequency of each DCT in order, you also can configure the timings manually.
Settings are: [Auto], [DCT0], [DCT1], [Both].