Foxconn P55A-S English Manual. - Page 33

► PCI IDE BusMaster This item is used to enable/disable PCI IDE busmaster function, BIOS use PCI busmastering for read/write to IDE drives. Fox Central Control Unit CMOS Setup Utility - Copyright (C) 1985-2009, American Megatrends, Inc. FOX Central Control Unit ► CPU Configuration [Press Enter] Help Item ► Voltage Options [Press Enter] ******* Ratio and Clock Setting ****** Configure CPU. Ratio Status:Unlocked (Min:09, Max:22) Ratio Actual Value:22 CPU Clock Ratio [22] ******* Memory Frequency ****** Current DRAM Speed :800MHz DRAM Frequency [Auto] Memory Timing by SPD [Auto] BIOS Write Protect [Enabled] 3 Move Enter:Select +/-/:Value F10:Save ESC:Exit F1:General Help F9:Optimized Defaults ► CPU Configuration / Voltage Options Press to go to its submenu. ► CPU Clock Ratio This item is used to set the ratio between CPU Core Clock and the FSB Frequency. You can use [+] or [-] to adjust the value. ► DRAM Frequency This item is used to set DRAM frequency. Setting values are: [Auto], [800 MHz], [1067 MHz], [1333 MHz]. ► Memory Timing by SPD This item is used to enable/disable provision of DRAM timing by SPD device. The Serial Presence Detect (SPD) device is a small EEPROM chip, mounted on a memory module. It contains important information about the module's speed, size, addressing mode and various other parameters, so that the motherboard memory controller (chipset) can better access the memory device. Select [Auto] for SPD enable mode. Select [Manual] to set the parameters by yourself. The following 10 settings are valid only when Memory Timing by SPD is set to [Manual]. ► DRAM tCL The number of memory clocks it takes a DRAM to return data after the read CAS_L is asserted depends on the memory clock frequency. The value that BIOS programs into the memory controller is a function of the target clock frequency. The target clock frequency is determined from the supported CAS latencies at given clock frequencies of each DIMM. ► DRAM tRAS (Active-to-Precharge Delay) This item allows you to set the minimum RAS# active time (in clock cycles). ► DRAM tRP (Precharge Command Period) 26