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Fujitsu MPC3096AT Product Manual - Page 25

Error Rate, Media Defects

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(4) Data assurance in the event of power failure Except for the data block being written to, the data on the disk media is assured in the event of any power supply abnormalities. This does not include power supply abnormalities during disk media initialization (formatting) or processing of defects (alternative block assignment). 1.8 Error Rate Known defects, for which alternative blocks can be assigned, are not included in the error rate count below. It is assumed that the data blocks to be accessed are evenly distributed on the disk media. (1) Unrecoverable read error Read errors that cannot be recovered by maximum 126 times read retries without user's retry and ECC corrections shall occur no more than 10 times when reading data of 1015 bits. Read retries are executed according to the disk drive's error recovery procedure, and include read retries accompanying head offset operations. (2) Positioning error Positioning (seek) errors that can be recovered by one retry shall occur no more than 10 times in 107 seek operations. 1.9 Media Defects Defective sectors are replaced with alternates when the disk is formatted prior to shipment from the factory (low level format). Thus, the host sees a defect-free device. Alternate sectors are automatically accessed by the disk drive. The user need not be concerned with access to alternate sectors. Chapter 6 describes the low level format at shipping. 1 - 10 C141-E055-01EN

Section	Page
Front title	1
PREFACE	4
CONTENTS	8
FIGURES	12
TABLES	14
CHAPTER 1 DEVICE OVERVIEW	16
1.1 Features	16
1.1.1 Functions and performance	16
1.1.2 Adaptability	17
1.1.3 Interface	17
1.2 Device Specifications	19
1.2.1 Specifications summary	19
1.2.2 Model and product number	20
1.3 Power Requirements	20
1.4 Environmental Specifications	23
1.5 Acoustic Noise	23
1.6 Shock and Vibration	24
1.7 Reliability	24
1.8 Error Rate	25
1.9 Media Defects	25
CHAPTER 2 DEVICE CONFIGURATION	26
2.1 Device Configuration	26
2.2 System Configuration	29
2.2.1 ATA interface	29
2.2.2 1 drive connection	29
2.2.3 2 drives connection	30
CHAPTER 3 INSTALLATION CONDITIONS	32
3.1 Dimensions	32
3.2 Mounting	34
3.3 Cable Connections	38
3.3.1 Device connector	38
3.3.2 Cable connector specifications	39
3.3.3 Device connection	39
3.3.4 Power supply connector (CN1)	40
3.4 Jumper Settings	40
3.4.1 Location of setting jumpers	40
3.4.2 Factory default setting	41
3.4.3 Jumper configuration	41
CHAPTER 4 THEORY OF DEVICE OPERATION	44
4.1 Outline	44
4.2 Subassemblies	44
4.2.1 Disk	44
4.2.2 Head	45
4.2.3 Spindle	46
4.2.4 Actuator	46
4.2.5 Air filter	46
4.3 Circuit Configuration	47
4.4 Power-on Sequence	49
4.5 Self-calibration	51
4.5.1 Self-calibration contents	51
4.5.2 Execution timing of self-calibration	52
4.5.3 Command processing during self-calibration	52
4.6 Read/write Circuit	53
4.6.1 Read/write preamplifier (PreAMP)	53
4.6.2 Write circuit	53
4.6.3 Read circuit	55
4.6.4 Time base generator circuit	56
4.7 Servo Control	57
4.7.1 Servo control circuit	57
4.7.2 Data-surface servo format	59
4.7.3 Servo frame format	60
4.7.4 Actuator motor control	61
4.7.5 Spindle motor control	62
CHAPTER 5 INTERFACE	64
5.1 Physical Interface	65
5.1.1 Interface signals	65
5.1.2 Signal assignment on the connector	66
5.2 Logical Interface	69
5.2.1 I/O registers	69
5.2.2 Command block registers	71
5.2.3 Control block registers	76
5.3 Host Commands	76
5.3.1 Command code and parameters	77
5.3.2 Command descriptions	79
5.3.3 Error posting	118
5.4 Command Protocol	119
5.4.1 Data transferring commands from device to host	119
5.4.2 Data transferring commands from host to device	121
5.4.3 Commands without data transfer	123
5.4.4 Other commands	124
5.4.5 DMA data transfer commands	124
5.5 Ultra DMA feature set	126
5.5.1 Overview	126
5.5.2 Phases of operation	127
5.5.3 Ultra DMA data in commands	127
5.5.3.1 Initiating an Ultra DMA data in burst	127
5.5.3.2 The data in transfer	128
5.5.3.3 Pausing an Ultra DMA data in burst	128
5.5.3.4 Terminating an Ultra DMA data in burst	129
5.5.4 Ultra DMA data out commands	131
5.5.4.1 Initiating an Ultra DMA data out burst	131
5.5.4.2 The data out transfer	132
5.5.4.3 Pausing an Ultra DMA data out burst	132
5.5.4.4 Terminating an Ultra DMA data out burst	133
5.5.5 Ultra DMA CRC rules	135
5.5.6 Series termination required for Ultra DMA	136
5.6 Timing	137
5.6.1 PIO data transfer	137
5.6.2 Single word DMA data transfer	139
5.6.3 Multiword data transfer	140
5.6.4 Ultra DMA data transfer	141
5.6.4.1 Initiating an Ultra DMA data in burst	141
5.6.4.2 Ultra DMA data burst timing requirements	142
5.6.4.3 Sustained Ultra DMA data in burst	144
5.6.4.4 Host pausing an Ultra DMA data in burst	145
5.6.4.5 Device terminating an Ultra DMA data in burst	146
5.6.4.6 Host terminating an Ultra DMA data in burst	147
5.6.4.7 Initiating an Ultra DMA data out burst	148
5.6.4.8 Sustained Ultra DMA data out burst	149
5.6.4.9 Device pausing an Ultra DMA data out burst	150
5.6.4.10 Host terminating an Ultra DMA data out burst	151
5.6.4.11 Device terminating an Ultra DMA data in burst	152
5.6.5 Power-on and reset	153
CHAPTER 6 OPERATIONS	154
6.1 Device Response to the Reset	154
6.1.1 Response to power-on	155
6.1.2 Response to hardware reset	156
6.1.3 Response to software reset	157
6.1.4 Response to diagnostic command	158
6.2 Address Translation	159
6.2.1 Default parameters	159
6.2.2 Logical address	160
6.3 Power Save	161
6.3.1 Power save mode	161
6.3.2 Power commands	163
6.4 Defect Management	163
6.4.1 Spare area	164
6.4.2 Alternating defective sectors	164
6.5 Read-Ahead Cache	166
6.5.1 Data buffer configuration	166
6.5.2 Caching operation	167
6.5.3 Usage of read segment	168
6.6 Write Cache	175
Addresses	177
Reader Comment Form	178