Gigabyte GA-7DXR User Manual - Page 103

AGP Mode, AGP Always Compensate, SDRAM ECC Setting, DRAM Timing setting by, DRAM PH Limit, DRAM Idle

Get Gigabyte GA-7DXR PDF manuals and user guides View all Gigabyte GA-7DXR manuals
Add to My Manuals
Save this manual to your list of manuals

Page 103 highlights

7DXR Motherboard • AGP Mode 4X 1X/2X Set AGP Mode to 4X (Only if the AGP Card support 4X Rate). (Default Value) Set AGP Mode to 1X/2X. • AGP Always Compensate Enabled Disabled Enable AGP Always Compensate function. (Default Value) Disable this function. • SDRAM ECC Setting Disabled Check Only Correct Error Correct + Scrub Disable DRAM ECC Setting function. (Default Value) Set DRAM ECC Setting to Check Only. Enable DRAM error checking function. Set DRAM ECC Setting to Correct Errors. Enable DRAM 1 bit error checking and correcting in CPU/AGP/PCI. Set DRAM ECC Setting to Correct+Scrub. Enable DRAM 1bit error checking and correcting in CPU/AGP/PCI and DRAM. • DRAM Timing setting by Auto Manual Set DRAM Timing setting to Auto. (Default value) Set DRAM Timing setting to Manual. • DRAM PH Limit This function specify the number of consecutive Page-Hit requests to allow before choosing a non-Page-Hit request. 1 Cycle 4 Cycle 8 Cycle 16 Cycle Set DRAM PH Limit to 1 Cycle. Set DRAM PH Limit to 4 Cycle. Set DRAM PH Limit to 8 Cycle. Set DRAM PH Limit to 16 Cycle. • DRAM Idle Limit This function specify the number of idle cycles to wait before precharging an idle bank.(Idle cycles are defined as cycles where no valid request is asserted to the MCT.) 0 Cycle 8 Cycle 12 Cycle Set DRAM Idle Limit to 0 Cycle. Set DRAM Idle Limit to 8 Cycle. Set DRAM Idle Limit to 12 Cycle. 97

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122
  • 123
  • 124
  • 125
  • 126
  • 127
  • 128
  • 129
  • 130
  • 131
  • 132
  • 133
  • 134
  • 135
  • 136
  • 137
  • 138
  • 139
  • 140
  • 141
  • 142
  • 143
  • 144
  • 145
  • 146
  • 147
7DXR Motherboard
97
•
AGP Mode
4X
Set AGP Mode to 4X (Only if the AGP Card support 4X Rate).
(Default Value)
1X/2X
Set AGP Mode to 1X/2X.
•
AGP Always Compensate
Enabled
Enable AGP Always Compensate function.
(Default Value)
Disabled
Disable this function.
•
SDRAM ECC Setting
Disabled
Disable DRAM ECC Setting function.
(Default Value)
Check Only
Set DRAM ECC Setting to Check Only. Enable DRAM error
checking function.
Correct Error
Set DRAM ECC Setting to Correct Errors. Enable DRAM 1 bit
error checking and correcting in CPU/AGP/PCI.
Correct + Scrub
Set DRAM ECC Setting to Correct+Scrub. Enable DRAM 1bit error
checking and correcting in CPU/AGP/PCI and DRAM.
•
DRAM Timing setting by
Auto
Set DRAM Timing setting to Auto.
(Default value)
Manual
Set DRAM Timing setting to Manual.
•
DRAM PH Limit
This function specify the number of consecutive Page-Hit requests to allow before
choosing a non-Page-Hit request.
1 Cycle
Set DRAM PH Limit to 1 Cycle.
4 Cycle
Set DRAM PH Limit to 4 Cycle.
8 Cycle
Set DRAM PH Limit to 8 Cycle.
16 Cycle
Set DRAM PH Limit to 16 Cycle.
•
DRAM Idle Limit
This function specify the number of idle cycles to wait before precharging an idle bank.(Idle
cycles are defined as cycles where no valid request is asserted to the MCT.)
0 Cycle
Set DRAM Idle Limit to 0 Cycle.
8 Cycle
Set DRAM Idle Limit to 8 Cycle.
12 Cycle
Set DRAM Idle Limit to 12 Cycle.