Gigabyte GA-7TCSV2 Manual - Page 30

Nehalem CPU Power Management

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Nehalem CPU Power Management BIOS Setup Figure 1-1-1: Nehalem CPU Power Management EIST (GV3) & C State Enabled Enable EIST (GV3) and C State items. (Default setting) Disabled Disable EIST (GV3) and C State items. EIST (GV3) Enabled Enable EIST (GV3. (Default setting) Disabled Disable EIST (GV3). EIST PSD Function HW_ALL In HW_ALL mode, the rpocessor hardware is responsible for coordinating the P-state among logical processors dependencies. The OS is responsible for keeping the P-state request up to date on all logical processors. (Default setting) SW_ALL In SW_ALL mode, the OS Power Manager is responsible for coordinating the P-state among loical processors with dependencies and must initiate the 30

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BIOS Setup
Nehalem CPU Power Management
Figure 1-1-1: Nehalem CPU Power Management
EIST (GV3) & C State
Enabled
Enable EIST (GV3) and C State items. (Default setting)
Disabled
Disable EIST (GV3) and C State items.
EIST (GV3)
Enabled
Enable EIST (GV3. (Default setting)
Disabled
Disable EIST (GV3).
EIST PSD Function
HW_ALL
In HW_ALL mode, the rpocessor hardware is responsible for coordinating
the P-state among logical processors dependencies. The OS is responsible
for keeping the P-state request up to date on all logical processors.
(Default setting)
SW_ALL
In SW_ALL mode, the OS Power Manager is responsible for coordinating
the P-state among loical processors with dependencies and must initiate the