HP ProLiant SL165s Memory technology evolution: an overview of system memory t - Page 17

Registered DIMMs., With DDR2 memory technology

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connect the memory controller to an Advanced Memory Buffer (AMB) chip that resides on each FB-DIMM, creating a point-to-point architecture. The outbound links transmit commands and write data to the FBDIMMs while the inbound links transmit read data back to the memory controller. The clock signal travels over a different set of pins. In addition to communicating over the outbound lanes, the memory controller communicates configuration information with each AMB over the System Management bus or SMBus. The AMB is an intelligent chip that manages serial communication with the memory controller and parallel communication with local DRAM devices. Each AMB receives signals for address, write data, and command information through the outbound links and re-transmits the signal to the next FB-DIMM on the channel. Each AMB decodes the command data and ignores the commands targeted for a different DIMM. The targeted AMB performs a read or write operation to local DRAM devices through a parallel interface. In a read operation, the AMB serializes data from the DRAM devices and transmits it to the memory controller through the inbound links. Figure 13. Serial communication between daisy-chained FB-DIMMs on a single channel Option NOTE: AMD Opteron™and Intel® Xeon® E55xx/X55xx CPU designs include the memory controller and clock functions integrated into processor module. When using DDR2-667 DRAM on the FB-DIMM, the peak theoretical throughput of the inbound links is 5.4 GB/s. The peak theoretical throughput of the outbound links is half that, approximately 2.6 GB/s. With DDR2 memory technology, manufacturers implemented FB-DIMMs as well as Unbuffered and Registered DIMMs. In spite of its advantages,however, FB-DIMM memory also costs more, uses more power, and has increased latency. As a result, the industry has not implemented FB-DIMMs for DDR3. Instead, engineers have increased server memory capacities by designing systems with Non-Uniform Memory Access (NUMA) architectures, which feature up to four memory channels for each CPU. 17

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connect the memory controller to an Advanced Memory Buffer (AMB) chip that resides on each FB-DIMM,
creating a point-to-point architecture. The outbound links transmit commands and write data to the FB-
DIMMs while the inbound links transmit read data back to the memory controller.
The clock signal travels over a different set of pins. In addition to communicating over the outbound lanes,
the memory controller communicates configuration information with each AMB over the System
Management bus or SMBus. The AMB is an intelligent chip that manages serial communication with the
memory controller and parallel communication with local DRAM devices. Each AMB receives signals for
address, write data, and command information through the outbound links and re-transmits the signal to the
next FB-DIMM on the channel. Each AMB decodes the command data and ignores the commands targeted
for a different DIMM. The targeted AMB performs a read or write operation to local DRAM devices through
a parallel interface. In a read operation, the AMB serializes data from the DRAM devices and transmits it to
the memory controller through the inbound links.
Figure 13
. Serial communication between daisy-chained FB-DIMMs on a single channel
Option
NOTE:
AMD Opteron™and Intel® Xeon® E55xx/X55xx CPU designs include the memory controller and clock
functions integrated into processor module.
When using DDR2-667 DRAM on the FB-DIMM, the peak theoretical throughput of the inbound links is
5.4 GB/s. The peak theoretical throughput of the outbound links is half that, approximately 2.6 GB/s.
With DDR2 memory technology, manufacturers implemented FB-DIMMs as well as Unbuffered and
Registered DIMMs.
In spite of its advantages,however, FB-DIMM memory also costs more, uses more
power, and has increased latency. As a result, the industry has not implemented FB-DIMMs for DDR3.
Instead, engineers have increased server memory capacities by designing systems with Non-Uniform
Memory Access (NUMA) architectures, which feature up to four memory channels for each CPU.
17