HP Vectra XE320 hp vectra xe320, technical reference manual - Page 36

POST Tests

Get HP Vectra XE320 PDF manuals and user guides View all HP Vectra XE320 manuals
Add to My Manuals
Save this manual to your list of manuals

Page 36 highlights

BIOS Overview POST Tests The POST is executed each time the system is powered on, or a reset is performed. The POST process verifies the basic functionality of the system components and initializes certain system parameters. The POST starts by displaying a graphic screen of the Hewlett-Packard logo when the PC is started. Devices, such as memory and newly installed hard disks, are configured automatically. The user is not requested to confirm the change. Newly removed hard disks are detected, and the user is prompted to confirm the new configuration by pressing F4. NOTE The POST does not detect when a hard disk drive has been otherwise changed. During the POST, the BIOS and other ROM data is copied into high-speed shadow RAM. The shadow RAM is addressed at the same physical location as the original ROM in a manner which is completely transparent to applications. It therefore appears to behave as very fast ROM. This technique provides faster access to the system BIOS firmware. The following table lists the POST checkpoint codes written at the start of each test: Checkpoint Code POST Routine Description D0 NMI is Disabled. CPU ID saved. Init code Checksum verification starting. D1 To do DMA init, Keyboard controller BAT test, start memory refresh and going to 4GB flat mode. D3 To start Memory sizing. D4 To comeback to real mode. Execute OEM patch. Set stack. D5 E000 ROM enabled. Init code is copied to segment 0 and control to be transferred to segment 0. D6 Control is in segment 0. To check key and verify main BIOS checksum. If either is pressed or main BIOS checksum is bad, go to check point E0 else go to check point D7. D7 To pass control to Interface Module. D8 Main BIOS runtime code is to be decompressed. D9 Control to be passed to main BIOS in shadow RAM. Boot Block Recovery Code Check Points. E0 OnBoard Floppy Controller (if any) is initialized. To start base 512K memory test. E1 To initialize interrupt vector table. E2 To initialize DMA and interrupt controllers. E6 To enable floppy and timer IRQ, enable internal cache. ED Initialize floppy drive. EE Start looking for a diskette in drive A: and read 1st sector of the diskette. EF Floppy read error. F0 Start searching 'AMIBOOT.ROM' file in root directory. F1 'AMIBOOT.ROM' file not present in root directory. F2 Start reading FAT table and analyze FAT to find the clusters occupied by 'AMIBOOT.ROM' file. F3 Start reading 'AMIBOOT.ROM' file cluster by cluster. F4 'AMIBOOT.ROM' file not of proper size. F5 Disable internal cache. FB Detect Flash type present. 36 XE320 product description

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
BIOS Overview
36
XE320 product description
POST Tests
The POST is executed each time the system is powered on, or a reset is performed. The POST process
verifies the basic functionality of the system components and initializes certain system parameters.
The POST starts by displaying a graphic screen of the Hewlett-Packard logo when the PC is started.
Devices, such as memory and newly installed hard disks, are configured automatically. The user is not
requested to confirm the change. Newly removed hard disks are detected, and the user is prompted to
confirm the new configuration by pressing
F4
.
NOTE
The POST does not detect when a hard disk drive has been otherwise changed.
During the POST, the BIOS and other ROM data is copied into high-speed shadow RAM. The shadow
RAM is addressed at the same physical location as the original ROM in a manner which is completely
transparent to applications. It therefore appears to behave as very fast ROM. This technique provides
faster access to the system BIOS firmware.
The following table lists the POST checkpoint codes written at the start of each test:
Checkpoint
Code
POST Routine Description
D0
NMI is Disabled. CPU ID saved. Init code Checksum verification starting.
D1
To do DMA init, Keyboard controller BAT test, start memory refresh and going to 4GB flat mode.
D3
To start Memory sizing.
D4
To comeback to real mode. Execute OEM patch. Set stack.
D5
E000 ROM enabled. Init code is copied to segment 0 and control to be transferred to segment 0.
D6
Control is in segment 0. To check
<CTRL><HOME>
key and verify main BIOS checksum. If either
<CTRL><HOME>
is pressed or main BIOS checksum is bad, go to check point E0 else go to check point D7.
D7
To pass control to Interface Module.
D8
Main BIOS runtime code is to be decompressed.
D9
Control to be passed to main BIOS in shadow RAM. Boot Block Recovery Code Check Points.
E0
OnBoard Floppy Controller (if any) is initialized. To start base 512K memory test.
E1
To initialize interrupt vector table.
E2
To initialize DMA and interrupt controllers.
E6
To enable floppy and timer IRQ, enable internal cache.
ED
Initialize floppy drive.
EE
Start looking for a diskette in drive A: and read 1st sector of the diskette.
EF
Floppy read error.
F0
Start searching '
AMIBOOT.ROM
' file in root directory.
F1
'
AMIBOOT.ROM
' file not present in root directory.
F2
Start reading FAT table and analyze FAT to find the clusters occupied by '
AMIBOOT.ROM
' file.
F3
Start reading '
AMIBOOT.ROM
' file cluster by cluster.
F4
'
AMIBOOT.ROM
' file not of proper size.
F5
Disable internal cache.
FB
Detect Flash type present.