HP Visualize b1000 hp Visualize b1000, c3000, c3600 workstations service handb - Page 68

start DIMM scan

Page 68 highlights

Troubleshooting Selftest Failures Table 3-2. Chassis Codes for B Class and C Class Workstations Ostat FLT FLT FLT FLT FLT FLT FLT FLT INI INI FLT FLT TST WRN FLT FLT TST WRN FLT TST Code FRU 5n00 SYS BD 5n02 SYS BD 5n04 SYS BD 5n07 SYS BD 5n08 SYS BD 5n0A SYS BD 5n0B SYS BD 5n0C SYS BD 7000 7002 7004 7005 7010 7011 7012 DIMM SYS BD SYS BD DIMM DIMM DIMM DIMM 7013 DIMM 7016 DIMM 7017 701F 7020 DIMM DIMM SYS BD Message Description unknown bus err path err assertd data parity err Runway dir error Runway broad err illegal response bus timeout CPU sync failure start DIMM scan init mem tables mem plt upd fail insufficient mem check DIMM order skip DIMM ord ck DIMM order error DIMM order error DIMM pair check skip mem pair ck no memory found search for IMM CPU n detected an unknown error on the system bus (Runway). CPU n detected a path error on the system bus (Runway). CPU n detected a data, address, or control parity error on the system bus (Runway). CPU n detected a directed error on the system bus (Runway). CPU n detected a broadcast error on the system bus (Runway). CPU n received data that did not match any outstanding data request. CPU n timed out before receiving requested data. The responder is logged in the system responder address. CPU n's synchronizer detected a rule violation on the system bus (Runway). Start looking for installed DIMMs. Initialize memory data structures. Error updating memory platform data. Insufficient memory detected to continue. Start memory DIMM order check. Bypass memory DIMM order check. Memory DIMMs are not in the proper order. Memory DIMMs are not in the proper order. As a result, the system cannot access one or more DIMMs and has deallocated all inaccessible DIMMs. Start memory DIMM pair check (DIMMs in a pair (e.g. 0a/0b) must match in J7xxx). Bypass memory DIMM set check. Memory scan couldn't find any DIMMs. Try to find a single memory bank to use for the initial memory module. 68 Chapter 3

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122
  • 123
  • 124
  • 125
  • 126
  • 127
  • 128
  • 129
  • 130
  • 131
  • 132
  • 133
  • 134
  • 135
  • 136
  • 137
  • 138
  • 139
  • 140
  • 141
  • 142
  • 143
  • 144
  • 145
  • 146
  • 147
  • 148
  • 149
  • 150
  • 151
  • 152
  • 153
  • 154
  • 155
  • 156
  • 157
  • 158
  • 159
  • 160
  • 161
  • 162
  • 163
  • 164
  • 165
  • 166
  • 167
  • 168
  • 169
  • 170
  • 171
  • 172
  • 173
  • 174
  • 175
  • 176
  • 177
  • 178
  • 179
  • 180
  • 181
  • 182
  • 183
  • 184
  • 185
  • 186
  • 187
  • 188
  • 189
  • 190
  • 191
  • 192
  • 193
  • 194
  • 195
  • 196
  • 197
  • 198
  • 199
  • 200
  • 201
  • 202
  • 203
  • 204
  • 205
  • 206
  • 207
  • 208
  • 209
  • 210
  • 211
  • 212
  • 213
  • 214
  • 215
  • 216
  • 217
  • 218
  • 219
  • 220
  • 221
  • 222
  • 223
  • 224
  • 225
  • 226
  • 227
  • 228
  • 229
  • 230
  • 231
  • 232
  • 233
  • 234
  • 235
  • 236
  • 237
  • 238
  • 239

68
Chapter 3
Troubleshooting
Selftest Failures
FLT
5
n
00
SYS BD
unknown bus err
CPU
n
detected an unknown error on the
system bus (Runway).
FLT
5
n
02
SYS BD
path err assertd
CPU
n
detected a path error on the
system bus (Runway).
FLT
5
n
04
SYS BD
data parity err
CPU
n
detected a data, address, or control
parity error on the system bus (Runway).
FLT
5
n
07
SYS BD
Runway dir error
CPU
n
detected a directed error on the
system bus (Runway).
FLT
5
n
08
SYS BD
Runway broad err
CPU
n
detected a broadcast error on the
system bus (Runway).
FLT
5
n
0A
SYS BD
illegal response
CPU
n
received data that did not match
any outstanding data request.
FLT
5
n
0B
SYS BD
bus timeout
CPU
n
timed out before receiving
requested data. The responder is logged in
the system responder address.
FLT
5
n
0C
SYS BD
CPU sync failure
CPU
n
’s synchronizer detected a rule
violation on the system bus (Runway).
INI
7000
DIMM
start DIMM scan
Start looking for installed DIMMs.
INI
7002
SYS BD
init mem tables
Initialize memory data structures.
FLT
7004
SYS BD
mem plt upd fail
Error updating memory platform data.
FLT
7005
DIMM
insufficient mem
Insufficient memory detected to continue.
TST
7010
DIMM
check DIMM order
Start memory DIMM order check.
WRN
7011
DIMM
skip DIMM ord ck
Bypass memory DIMM order check.
FLT
7012
DIMM
DIMM order error
Memory DIMMs are not in the proper
order.
FLT
7013
DIMM
DIMM order error
Memory DIMMs are not in the proper
order. As a result, the system cannot
access one or more DIMMs and has
deallocated all inaccessible DIMMs.
TST
7016
DIMM
DIMM pair check
Start memory DIMM pair check (DIMMs
in a pair (e.g. 0a/0b) must match in
J7xxx).
WRN
7017
DIMM
skip mem pair ck
Bypass memory DIMM set check.
FLT
701F
DIMM
no memory found
Memory scan couldn’t find any DIMMs.
TST
7020
SYS BD
search for IMM
Try to find a single memory bank to use
for the initial memory module.
Table 3-2. Chassis Codes for B Class and C Class Workstations
Ostat
Code
FRU
Message
Description