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Hitachi HTS542525K9SA00 Specifications - Page 26

Data sheet, World Wide Name Assignment, Drive organization - model number

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4.2 Data sheet Table 2: Mechanical positioning performance Description Data transfer rates (Mbps) Interface transfer rates (Mb/s) Data buffer size1 (KB) Rotational speed (RPM) Number of buffer segments (read) Number of buffer segments (write) Recording density - max (Kbpi) Track density [TPI] Areal density - max (Gbits/in2 ) Number of data bands 80GB Model 966 900 135 120 120GB Model 160GB Model 824 966 133 (PATA) / 300 (SATA) 2048 (80GB & 160GB), 8192 7200 up to 128 up to 63 733 900 125 135 92 120 30 4.3 World Wide Name Assignment Table 3: Word Wide Name Assignment Description 80 GB model 120 GB model 160 GB model Organization Hitachi GST Manufacturing Site Excelstor Plant China / Hitachi GST China Plant (GSP) Product Deskstar 7K160 OUI 000CCAh SHBU Block Assignment 320h for ExcelStor,China 324h for Hitachi GST China Plant 326h for ExcelStor,China 328h for Hitachi 321h for ExcelStor,China 325h for Hitachi GST China Plant Port/Node ID 11b 4.4 Drive organization 4.4.1 Drive format Upon shipment from manufacturing the drive satisfies the sector continuity in the physical format by means of the defect flagging strategy described in Section 5.0, "Defect flagging strategy" on page 21 in order to provide the maximum performance to users. Deskstar 7K160 Hard Disk Drive Specification 12

Section	Page
1.0 General	15
1.1 Introduction	15
1.2 References	15
1.3 Abbreviations	15
1.4 Caution	17
2.0 General features of the drive	19
3.0 Fixed-disk subsystem description	23
3.1 Control electronics	23
3.2 Head disk assembly	23
3.3 Actuator	23
4.0 Drive characteristics	25
4.1 Default logical drive parameters	25
4.2 Data sheet	26
4.3 World Wide Name Assignment	26
4.4 Drive organization	26
4.4.1 Drive format	26
4.4.2 Cylinder allocation	27
4.5 Performance characteristics	29
4.5.1 Command overhead	29
4.5.2 Mechanical positioning	29
4.5.3 Drive ready time	31
4.5.4 Operating modes	31
5.0 Defect flagging strategy	33
6.0 Electrical interface specification	35
6.1 Connector location	35
6.1.1 4 pin DC power connector	36
6.1.2 AT signal connector	36
6.2 Signal definitions (PATA model)	37
6.3 Signal descriptions	38
6.4 Interface logic signal levels (pata model)	41
6.5 Signal definition (SATA model)	41
6.5.1 TX+ / TX-	41
6.5.2 RX+ / RX-	42
6.5.3 Out of band signaling (SATA model)	42
6.6 Reset timings	43
6.7 PIO timings	44
6.7.1 Write DRQ interval time	44
6.7.2 Read DRQ interval time	44
6.8 Multi-word DMA timings	45
6.9 Ultra DMA timings	46
6.9.1 Initiating Read DMA	46
6.9.2 Host Pausing Read DMA	47
6.9.3 Host Terminating Read DMA	48
6.9.4 Device Terminating Read DMA	49
6.9.5 Initiating Write DMA	50
6.9.6 Device Pausing Write DMA	51
6.9.7 Device Terminating Write DMA	52
6.9.8 Host Terminating Write DMA	53
6.10 Addressing of registers	54
6.10.1 Cabling	54
7.0 Specification	57
7.1 Jumper settings	57
7.1.1 Jumper pin location	57
7.1.2 Jumper pin identification	57
7.1.3 Jumper pin assignment	58
7.1.4 Jumper positions	59
7.2 Environment	63
7.2.1 Temperature and humidity	63
7.2.2 Corrosion test	64
7.3 DC power requirements	64
7.3.1 Input voltage	65
7.3.2 Power supply current (typical)	66
7.3.3 Power supply generated ripple at drive power connector	67
7.4 Reliability	68
7.4.1 Data integrity	68
7.4.2 Cable noise interference	68
7.4.3 Start/stop cycles	68
7.4.4 Preventive maintenance	68
7.4.5 Data reliability	68
7.4.6 Required power-off sequence	68
7.5 Mechanical specifications	69
7.5.1 Physical dimensions and weight	69
7.5.2 Mounting hole locations	70
7.5.3 Connector locations	71
7.5.4 Drive mounting	72
7.5.5 Heads unload and actuator lock	72
7.6 Vibration and shock	73
7.6.1 Operating vibration	73
7.6.2 Nonoperating vibration	73
7.6.3 Operating shock	74
7.6.4 Nonoperating shock	74
7.6.5 Nonoperating rotational shock	74
7.7 Acoustics	75
7.8 Identification labels	75
7.9 Safety	76
7.9.1 UL and CSA approval	76
7.9.2 German safety mark	76
7.9.3 Flammability	76
7.9.4 Safe handling	76
7.9.5 Environment	76
7.9.6 Secondary circuit protection	76
7.10 Electromagnetic compatibility	77
7.10.1 CE Mark	77
7.10.2 C-TICK mark	77
7.10.3 BSMI mark	77
7.10.4 MIC Mark	77
7.11 Packaging	77
7.11.1 Substance restriction requirements	77
8.0 General	79
8.1 Introduction	79
8.2 Terminology	79
8.3 Deviations from standard	79
9.0 Registers	81
9.1 Register set	81
9.2 Alternate Status Register	82
9.3 Command Register	82
9.4 Cylinder High Register	82
9.5 Cylinder Low Register	82
9.6 Data Register	83
9.7 Device Control Register	83
9.8 Drive Address Register	84
9.9 Device/Head Register	84
9.10 Error Register	85
9.11 Features Register	85
9.12 Sector Count Register	85
9.13 Sector Number Register	86
9.14 Status Register	86
10.0 General operation	89
10.1 Reset response	89
10.2 Register initialization	90
10.3 Diagnostic and Reset considerations	91
10.4 Sector Addressing Mode	92
10.4.1 Logical CHS addressing mode	92
10.4.2 LBA addressing mode	92
10.5 Power management features	93
10.5.1 Power mode	93
10.5.2 Power management commands	93
10.5.3 Standby timer	93
10.5.4 Interface capability for power modes	94
10.6 S.M.A.R.T. Function	95
10.6.1 Attributes	95
10.6.2 Attribute values	95
10.6.3 Attribute thresholds	95
10.6.4 Threshold exceeded condition	95
10.6.5 S.M.A.R.T. commands	95
10.6.6 Off-line read scanning	95
10.6.7 Error log	96
10.6.8 Self-test	96
10.7 Security Mode Feature Set	97
10.7.1 Security mode	97
10.7.2 Security level	97
10.7.3 Passwords	98
10.7.4 Operation example	98
10.7.5 Command table	102
10.8 Host Protected Area Feature	104
10.8.1 Example for operation (In LBA Mode)	104
10.8.2 Security extensions	105
10.9 Seek overlap	106
10.10 Write cache function	107
10.11 Reassign function	108
10.11.1 Auto Reassign function	108
10.12 Power-Up in Standby feature set	109
10.13 Advanced Power Management feature set (APM)	110
10.14 Automatic Acoustic Management feature set (AAM)	111
10.15 Address Offset Feature	112
10.15.1 Enable/Disable Address Offset Mode	112
10.15.2 Identify Device Data	113
10.15.3 Exceptions in Address Offset Mode	113
10.16 48-bit Address Feature Set	114
10.17 Streaming feature Set	114
10.17.1 Streaming commands	115
10.17.2 Urgent bit	115
10.17.3 Flush to Disk bit	115
10.17.4 Not Sequential bit	115
10.17.5 Read Continuous bit	116
10.17.6 Write Continuous bit	116
10.17.7 Handle Streaming Error bit	116
10.17.8 Streaming Logs	116
10.18 SATA BIST (Built-in Self Test)	116
10.19 SATA Interface Power Management	116
10.20 Software Setting Preservation	116
10.20.1 COMRESET Preservation Requirements	117
10.21 SATA II Optional Features	118
10.21.1 Asynchronous Signal Recovery	118
10.21.2 Device Power Connector Pin 11 Definition	118
10.21.3 Phy Event Counters	118
10.21.4 READ LOG EXT Log Page 11h	120
10.22 SCT Command Transport Feature Set	121
10.22.1 SCT Command Protocol	122
10.22.2 SCT Command Set	130
11.0 Command protocol	141
11.1 PIO Data In commands	141
11.2 PIO Data Out Commands	142
11.3 Non-data commands	144
11.4 DMA commands	145
12.0 Command descriptions	147
12.1 Check Power Mode (E5h/98h)	152
12.2 Configure Stream (51h)	153
12.3 Device Configuration Overlay (B1h)	155
12.3.1 DEVICE CONFIGURATION RESTORE (Subcommand C0h)	155
12.3.2 DEVICE CONFIGURATION FREEZE LOCK (subcommand C1h)	155
12.3.3 DEVICE CONFIGURATION IDENTIFY (subcommand C2h)	156
12.3.4 DEVICE CONFIGURATION SET (subcommand C3h)	156
12.4 Download Microcode (92h)	159
12.5 Execute Device Diagnostic (90h)	161
12.6 Flush Cache (E7h)	162
12.7 Flush Cache Ext (EAh)	163
12.8 Format Track (50h)	164
12.9 Format Unit (F7h)	166
12.10 Identify Device (ECh)	167
12.11 Idle (E3h/97h)	178
12.12 Idle Immediate (E1h/95h)	179
12.13 Initialize Device Parameters (91h)	180
12.14 Read Buffer (E4h)	181
12.15 Read DMA (C8h/C9h)	182
12.16 Read DMA Ext (25h)	184
12.17 Read Log Ext (2Fh)	186
12.17.1 General Purpose Log Directory	188
12.17.2 Extended Comprehensive SMART Error Log	189
12.17.3 Extended Self-test log sector	191
12.17.4 Read Stream Error Log	192
12.17.5 Write Stream Error Log	194
12.17.6 Streaming Performance Log	195
12.18 Read Long (22h/23h)	197
12.19 Read Multiple (C4h)	199
12.20 Read Multiple Ext (29h)	200
12.21 Read Native Max ADDRESS (F8h)	202
12.22 Read Native Max Address Ext (27h)	203
12.23 Read Sectors (20h/21h)	204
12.24 Read Sector(s) Ext (24h)	206
12.25 Read Stream DMA (2Ah)	208
12.26 Read Stream PIO (2Bh)	212
12.27 Read Verify Sectors (40h/41h)	215
12.28 Read Verify Sectors Ext (42h)	217
12.29 Recalibrate (1xh)	219
12.30 Security Disable Password (F6h)	220
12.31 Security Erase Prepare	221
12.32 Security Erase Unit (F4h)	222
12.33 Security Freeze Lock (F5h)	224
12.34 Security Set Password (F1h)	225
12.35 Security Unlock (F2h)	227
12.36 Seek (7xh)	229
12.37 Set Features (EFh)	230
12.37.1 Set Transfer mode	231
12.37.2 Write Cache	231
12.37.3 Advanced Power Management	231
12.37.4 Automatic Acoustic Management	233
12.38 Set Max ADDRESS (F9h)	234
12.38.1 Set Max Set Password (Feature=01h)	236
12.38.2 Set Max Lock (Feature=02h)	237
12.38.3 Set Max Unlock (Feature = 03h)	238
12.38.4 Set Max Freeze Lock (Feature = 04h)	239
12.39 Set Max Address Ext (37h)	240
12.40 Set Multiple (C6h)	242
12.41 Sleep (E6h/99h)	243
12.42 S.M.A.R.T. Function Set (B0h)	244
12.42.1 S.M.A.R.T. Function Subcommands	245
12.42.2 Device Attribute Data Structure	249
12.42.3 Device Attribute Thresholds data structure	252
12.42.4 S.M.A.R.T. Log Directory	254
12.42.5 S.M.A.R.T. summary error log sector	254
12.42.6 Self-test log data structure	256
12.42.7 Selective self-test log data structure	257
12.42.8 Error reporting	258
12.43 Standby (E2h/96h)	260
12.44 Standby Immediate (E0h/94h)	262
12.45 Write Buffer (E8h)	263
12.46 Write DMA (CAh/CBh)	264
12.47 Write DMA Ext (35h)	266
12.48 Write DMA FUA Ext (3Dh)	268
12.49 Write Log Ext (3Fh)	270
12.50 Write Long (32h/33h)	271
12.51 Write Multiple (C5h)	273
12.52 Write Multiple Ext (39h)	275
12.53 Writer Multiple FUA Ext (CEh)	277
12.54 Write Sectors (30h/31h)	279
12.55 Write Sector(s) Ext (34h)	281
12.56 Write Stream DMA (3Ah)	283
12.57 Write Stream PIO (3Bh)	285