Intel D845PEMY Product Specification - Page 18

Intel, 845PE Chipset

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Intel Desktop Board D845PEMY Technical Product Specification 1.7 Intel® 845PE Chipset The Intel 845PE chipset consists of the following devices: • Intel 82845PE Memory Controller Hub (MCH) with Accelerated Hub Architecture (AHA) bus • Intel 82801DB I/O Controller Hub (ICH4) with AHA bus • Firmware Hub (FWH) The MCH is a centralized controller for the system bus, the memory bus, the AGP bus, and the Accelerated Hub Architecture interface. The ICH4 is a centralized controller for the board's I/O paths. The FWH provides the nonvolatile storage of the BIOS. For information about The Intel 845PE chipset Resources used by the chipset Refer to http://developer.intel.com/ Chapter 2 1.7.1 AGP The AGP connector supports AGP add-in cards with 1.5 V Switching Voltage Level (SVL). Legacy 3.3 V AGP cards are not supported. For information about The location of the AGP connector Refer to Figure 1, page 12 NOTE Install memory in the DIMM sockets prior to installing the AGP video card to avoid interference with the memory retention mechanism. NOTE The AGP connector is keyed for 1.5 V AGP cards only. Do not attempt to install a legacy 3.3 V AGP card. The AGP connector is not mechanically compatible with legacy 3.3 V AGP cards. AGP is a high-performance interface for graphics-intensive applications, such as 3D applications. While based on the PCI Local Bus Specification, Rev. 2.2, AGP is independent of the PCI bus and is intended for exclusive use with graphical display devices. AGP overcomes certain limitations of the PCI bus related to handling large amounts of graphics data with the following features: • Pipelined memory read and write operations that hide memory access latency • Demultiplexing of address and data on the bus for nearly 100 percent efficiency 18

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Intel Desktop Board D845PEMY Technical Product Specification
18
1.7 Intel
®
845PE Chipset
The Intel 845PE chipset consists of the following devices:
•
Intel 82845PE Memory Controller Hub (MCH) with Accelerated Hub Architecture (AHA) bus
•
Intel 82801DB I/O Controller Hub (ICH4) with AHA bus
•
Firmware Hub (FWH)
The MCH is a centralized controller for the system bus, the memory bus, the AGP bus, and the
Accelerated Hub Architecture interface.
The ICH4 is a centralized controller for the board’s I/O
paths.
The FWH provides the nonvolatile storage of the BIOS.
For information about
Refer to
The Intel 845PE chipset
Resources used by the chipset
Chapter 2
1.7.1
AGP
The AGP connector supports AGP add-in cards with 1.5 V Switching Voltage Level (SVL).
Legacy 3.3 V AGP cards are not supported.
For information about
Refer to
The location of the AGP connector
Figure 1, page 12
±
NOTE
Install memory in the DIMM sockets prior to installing the AGP video card to avoid interference
with the memory retention mechanism.
±
NOTE
The AGP connector is keyed for 1.5 V AGP cards only.
Do not attempt to install a legacy 3.3 V
AGP card.
The AGP connector is not mechanically compatible with legacy 3.3 V AGP cards.
AGP is a high-performance interface for graphics-intensive applications, such as 3D applications.
While based on the
PCI Local Bus Specification
, Rev. 2.2, AGP is independent of the PCI bus and
is intended for exclusive use with graphical display devices.
AGP overcomes certain limitations of
the PCI bus related to handling large amounts of graphics data with the following features:
•
Pipelined memory read and write operations that hide memory access latency
•
Demultiplexing of address and data on the bus for nearly 100 percent efficiency