Home » Intel Manuals » Motherboards » Intel D915PCM » Manual Viewer

Intel D915PCM Product Specification - Page 25

Intel, 915P Chipset - d915pcy drivers

Get Intel D915PCM PDF manuals and user guides

Add to My Manuals
Save this manual to your list of manuals

Page 25 highlights

Product Description 1.7 Intel® 915P Chipset The Intel 915P chipset consists of the following devices: • Intel 82915P Memory Controller Hub (MCH) with Direct Media Interface (DMI) interconnect • Intel 82801FB I/O Controller Hub (ICH6) with DMI interconnect • Firmware Hub (FWH) The MCH is a centralized controller for the system bus, the memory bus, the PCI Express bus, and the DMI interconnect. The ICH6 is a centralized controller for the board's I/O paths. The FWH provides the nonvolatile storage of the BIOS. For information about The Intel 915P chipset Resources used by the chipset Refer to http://developer.intel.com/ Chapter 2 1.7.1 USB The boards support up to eight USB 2.0 ports, supports UHCI and EHCI, and uses UHCI- and EHCI-compatible drivers. The ICH6 provides the USB controller for all ports. The port arrangement is as follows: • Four ports are implemented with dual stacked back panel connectors adjacent to the audio connectors • Four ports are routed to two separate front panel USB connectors NOTE Computer systems that have an unshielded cable attached to a USB port may not meet FCC Class B requirements, even if no device is attached to the cable. Use shielded cable that meets the requirements for full-speed devices. For information about The location of the USB connectors on the back panel The location of the front panel USB connectors on the D915PCY board The location of the front panel USB connectors on the D915PCM board Refer to Figure 17, page 58 Figure 18, page 60 Figure 19, page 62 1.7.2 IDE Support The boards provides five IDE interface connectors: • One parallel ATA IDE connector that supports two devices • Four serial ATA IDE connectors that support one device per connector 1.7.2.1 Parallel ATE IDE Interface The ICH6's Parallel ATA IDE controller has one bus-mastering Parallel ATA IDE interface. The Parallel ATA IDE interface supports the following modes: • Programmed I/O (PIO): processor controls data transfer. • 8237-style DMA: DMA offloads the processor, supporting transfer rates of up to 16 MB/sec. 25

Section	Page
Intel® Desktop Boards D915PCY/D915PCM Technical Product Specification	1
Revision History	2
Preface	3
Intended Audience	3
What This Document Contains	3
Typographical Conventions	3
Other Common Notation	4
Contents	5
1 Product Description	11
1.1 PCI Bus Terminology Change	11
1.2 Board Differences	11
1.3 Overview	12
1.3.1 Feature Summary	12
1.3.2 Manufacturing Options	13
1.3.3 Board Layouts	14
1.3.4 Block Diagram	18
1.4 Online Support	19
1.5 Processor	19
1.6 System Memory	20
1.6.1 Memory Configurations	21
1.6.1.1 Dual Channel (Interleaved) Mode Configurations	22
1.6.1.2 Single Channel (Asymmetric) Mode Configurations	24
1.7 Intel® 915P Chipset	25
1.7.1 USB	25
1.7.2 IDE Support	25
1.7.2.1 Parallel ATE IDE Interface	25
1.7.2.2 Serial ATA Interfaces	26
1.7.2.3 SCSI Hard Drive Activity LED Connector (Optional)	27
1.7.3 Real-Time Clock, CMOS SRAM, and Battery	27
1.8 PCI Express Connectors	27
1.9 I/O Controller	28
1.9.1 Serial Ports	28
1.9.2 Parallel Port	28
1.9.3 Diskette Drive Controller	28
1.9.4 Keyboard and Mouse Interface	28
1.10 Audio Subsystem	29
1.10.1 Audio Subsystem Software	29
1.10.2 Audio Connectors	29
1.10.3 Intel® High Definition Audio Subsystem	30
1.11 LAN Subsystem	31
1.11.1 Intel® 82562EZ Physical Layer Interface Device	31
1.11.1.1 RJ-45 LAN Connector with Integrated LEDs	32
1.11.2 Alert Standard Format (ASF) Support	32
1.11.3 LAN Subsystem Software	33
1.11.4 Intel® Wireless Connect Technology (Optional)	33
1.12 Hardware Management Subsystem	33
1.12.1 Hardware Monitoring and Fan Control ASIC	33
1.12.2 Thermal Monitoring	34
1.12.3 Fan Monitoring	35
1.12.4 Chassis Intrusion and Detection	36
1.13 Power Management	36
1.13.1 ACPI	36
1.13.1.1 System States and Power States	37
1.13.1.2 Wake-up Devices and Events	39
1.13.2 Hardware Support	39
1.13.2.1 Power Connector	40
1.13.2.2 Fan Connectors	40
1.13.2.3 LAN Wake Capabilities	41
1.13.2.4 Instantly Available PC Technology	41
1.13.2.5 Resume on Ring	42
1.13.2.6 Wake from USB	42
1.13.2.7 Wake from PS/2 Devices	42
1.13.2.8 PME# Signal Wake-up Support	42
1.13.2.9 WAKE# Signal Wake-up Support	42
1.13.2.10 +5 V Standby Power Indicator LED	43
1.14 Trusted Platform Module (Optional)	44
1.14.1 System Requirements	44
1.14.2 Warning of Potential Data Loss	44
1.14.3 Security Precautions	45
1.14.3.1 Password Procedures	45
1.14.3.2 Emergency Recovery File Back Up Procedures	46
1.14.3.3 Hard Drive Image Backup Procedures	46
1.14.3.4 Clear Text Backup (Optional)	46
1.14.4 Trusted Platform Module Ownership	46
1.14.5 Enabling the Trusted Platform Module	47
1.14.6 Assuming Trusted Platform Module Ownership	47
1.14.7 Recovery Procedures	48
1.14.7.1 Recovering from Hard Disk Failure	48
1.14.7.2 Recovering from Desktop Board or TPM Failure	48
1.14.8 Clearing Trusted Platform Module Ownership	49
1.14.9 Software Support	50
2 Technical Reference	51
2.1 Introduction	51
2.2 Memory Resources	51
2.2.1 Addressable Memory	51
2.2.2 Memory Map	53
2.3 DMA Channels	53
2.4 Fixed I/O Map	54
2.5 PCI Configuration Space Map	55
2.6 Interrupts	56
2.7 PCI Conventional Interrupt Routing Map	56
2.8 Connectors	58
2.8.1 Back Panel Connectors	58
2.8.2 Component-side Connectors	60
2.8.2.1 Chassis Fan Connectors	65
2.8.2.2 Power Supply Connectors	66
2.8.2.3 Add-in Card Connectors	67
2.8.2.4 Auxiliary Front Panel Power/Sleep LED Connector	68
2.8.2.5 Front Panel Connector	68
2.8.2.5.1 Hard Drive Activity LED Connector [Yellow]	69
2.8.2.5.2 Reset Switch Connector [Purple]	69
2.8.2.5.3 Power/Sleep LED Connector [Green]	69
2.8.2.5.4 Power Switch Connector [Red]	69
2.8.2.6 Front Panel USB Connectors	69
2.8.2.7 Front Panel IEEE 1394a Connectors (Optional)	70
2.9 Jumper Block	71
2.10 Mechanical Considerations	72
2.10.1 D915PCY Board Form Factor	72
2.10.2 D915PCM Board Form Factor	73
2.10.3 I/O Shield	74
2.11 Electrical Considerations	75
2.11.1 DC Loading	75
2.11.2 Add-in Board Considerations	75
2.11.3 Fan Connector Current Capability	76
2.11.4 Power Supply Considerations	76
2.12 Thermal Considerations	77
2.13 Reliability	79
2.14 Environmental	80
2.15 Regulatory Compliance	80
2.15.1 Safety Regulations	80
2.15.2 EMC Regulations	81
2.15.2.1 FCC Compliance Statement (USA)	81
2.15.2.2 Canadian Compliance Statement	82
2.15.3 European Union Declaration of Conformity Statement	82
2.15.4 Product Ecology Statements	82
2.15.4.1 Disposal Considerations	83
2.15.4.2 Recycling Considerations	83
2.15.5 Product Certification Markings (Board Level)	83
3 Overview of BIOS Features	85
3.1 Introduction	85
3.2 BIOS Flash Memory Organization	86
3.3 Resource Configuration	86
3.3.1 PCI Autoconfiguration	86
3.3.2 PCI IDE Support	86
3.4 System Management BIOS (SMBIOS)	87
3.5 Legacy USB Support	87
3.6 BIOS Updates	88
3.6.1 Language Support	88
3.6.2 Custom Splash Screen	88
3.7 Boot Options	89
3.7.1 CD-ROM Boot	89
3.7.2 Network Boot	89
3.7.3 Booting Without Attached Devices	89
3.7.4 Changing the Default Boot Device During POST	89
3.8 Fast Booting Systems with Intel® Rapid BIOS Boot	90
3.8.1 Peripheral Selection and Configuration	90
3.8.2 Intel Rapid BIOS Boot	90
3.9 BIOS Security Features	91
4 Error Messages and Beep Codes	93
4.1 BIOS Error Messages	93
4.2 Port 80h POST Codes	95
4.3 Bus Initialization Checkpoints	99
4.4 Speaker	100

Match case Limit results 1 per page

Product Description

1.7 Intel

915P Chipset

The Intel 915P chipset consists of the following devices:

•

Intel 82915P Memory Controller Hub (MCH) with Direct Media Interface (DMI) interconnect

•

Intel 82801FB I/O Controller Hub (ICH6) with DMI interconnect

•

Firmware Hub (FWH)

The MCH is a centralized controller for the system bus, the memory bus, the PCI Express bus, and

the DMI interconnect.

The ICH6 is a centralized controller for the board’s I/O paths.

The FWH

provides the nonvolatile storage of the BIOS.

For information about

Refer to

The Intel 915P chipset

http://developer.intel.com/

Resources used by the chipset

Chapter 2

1.7.1

USB

The boards support up to eight USB 2.0 ports, supports UHCI and EHCI, and uses UHCI- and

EHCI-compatible drivers.

The ICH6 provides the USB controller for all ports.

The port arrangement is as follows:

•

Four ports are implemented with dual stacked back panel connectors adjacent to the audio

connectors

•

Four ports are routed to two separate front panel USB connectors

NOTE

Computer systems that have an unshielded cable attached to a USB port may not meet FCC

Class B requirements, even if no device is attached to the cable.

Use shielded cable that meets the

requirements for full-speed devices.

For information about

Refer to

The location of the USB connectors on the back panel

Figure 17, page 58

The location of the front panel USB connectors on the D915PCY board

Figure 18, page 60

The location of the front panel USB connectors on the D915PCM board

Figure 19, page 62

1.7.2

IDE Support

The boards provides five IDE interface connectors:

•

One parallel ATA IDE connector that supports two devices

•

Four serial ATA IDE connectors that support one device per connector

1.7.2.1

Parallel ATE IDE Interface

The ICH6’s Parallel ATA IDE controller has one bus-mastering Parallel ATA IDE interface.

The

Parallel ATA IDE interface supports the following modes:

•

Programmed I/O (PIO):

processor controls data transfer.

•

8237-style DMA:

DMA offloads the processor, supporting transfer rates of up to 16 MB/sec.