Intel MFS2600KI Technical Product Specification - Page 36

Appendix A: Integration and Usage Tips

Intel® Compute Module MFS5000SI TPS

Appendix A: Integration and Usage Tips

±

When two processors are installed, both must be of identical revision, core voltage, and bus/core

speed. Mixed processor steppings is supported. However, the stepping of one processor cannot

be greater than one stepping back of the other.

±

Processors must be installed in order. CPU 1 is located near the edge of the server board and

must be populated to operate the board.

±

Only Fully Buffered DIMMs (FBD) are supported on this server board.

±

Mixing memory type, size, speed, rank and/or memory vendors is not validated and is not

supported on this server board.

±

Non-ECC memory is not validated and is not supported in a server environment

±

For a list of supported memory for this server board, see the

Intel

®

Compute Module MFS5000SI

Tested Memory List

in the Intel

®

Server Configurator Tool.

±

For a list of Intel supported operating systems, add-in cards, and peripherals for this server

board, see the

Intel

®

Compute Module MFS5000SI Tested Hardware and Operating System List.

±

Only Dual-Core processors 5100 sequence or Quad-Core Intel

®

Xeon

®

processors 5300 or 5400

sequence, with system bus speeds of 1066/1333 MHz are supported on this server board.

Previous generation Intel

®

Xeon

®

processors are not supported.

±

For best performance, the number of DIMMs installed should be balanced across both memory

branches. For example, a four-DIMM configuration will perform better than a two-DIMM

configuration and should be installed in DIMM Slots A1, B1, C1, and D1. An eight-DIMM

configuration will perform better than a six-DIMM configuration.

±

Normal Integrated BMC functionality (for example, KVM, monitoring, and remote media) is

disabled with the force BMC update jumper set to the “enabled” position (pins 1-2). The server

should never be run with the BMC force update jumper set in this position and should only be

used when the standard firmware update process fails. This jumper should remain in the default

(disabled) position (pins 2-3) when the compute module is running normally.

±

When performing the BIOS update procedure, the BIOS select jumper must be set to its default

position (pins 2-3).

Revision 1.4

Intel order number: E15154-007

30

Section	Page
1. Introduction	7
1.1 Chapter Outline	7
1.2 Intel® Compute Module Use Disclaimer	7
2. Product Overview	8
2.1 Intel® Compute Module MFS5000SI Feature Set	8
2.2 Compute Module Layout	9
2.2.1 Connector and Component Locations	9
2.2.2 External I/O Connector Locations	10
2.2.3 Compute Module Mechanical Drawings	11
3. Functional Architecture	12
3.1 Intel® 5000P Memory Controller Hub (MCH)	13
3.1.1 System Bus Interface	13
3.1.2 Processor Support	13
3.1.2.1 Processor Population Rules	13
3.1.2.2 Common Enabling Kit (CEK) Design Support	14
3.1.3 Memory Subsystem	14
3.1.3.1 Memory RASUM Features	15
3.1.3.2 Supported and Nonsupported Memory Configurations	16
3.1.3.3 DIMM Population Rules and Supported DIMM Configurations	16
3.1.3.3.1 Minimum Non-Mirrored Mode Configuration	17
3.1.3.4 Non-mirrored Mode Memory Upgrades	18
3.1.3.4.1 Mirrored Mode Memory Configuration	19
3.1.3.4.2 DIMM Sparing Mode Memory Configuration	19
3.1.3.4.2.1 Single Branch Mode Sparing	20
3.1.3.4.2.2 Dual Branch Mode Sparing	20
3.2 Intel® 6321ESB I/O Controller Hub	22
3.2.1 PCI Subsystem	22
3.2.1.1 PCI32: 32-bit, 33-MHz PCI Bus Segment	23
3.2.1.2 PXA: 64-bit, 133MHz PCI-X Bus Segment	23
3.2.1.3 PE1: One x4 PCI Express* Bus Segment	23
3.2.1.4 PE2: One x4 PCI Express* Bus Segment	23
3.2.1.5 PE4, PE5: Two x4 PCI Express* Bus Segments	23
3.2.1.6 PE6, PE7: Two x4 PCI Express* Bus Segments	23
3.2.2 Serial ATA Support	23
3.2.3 Parallel ATA (PATA) Support	23
3.2.4 USB 2.0 Support	24
3.3 Video Support	24
3.3.1.1 Video Modes	24
3.3.1.2 Video Memory Interface	24
3.4 Network Interface Controller (NIC)	25
3.4.1 Intel® I/O Acceleration Technology	25
3.4.2 MAC Address Definition	25
3.5 Super I/O	25
3.5.1.1 Serial Ports	25
3.5.1.2 Floppy Disk Controller	26
3.5.1.3 Keyboard and Mouse Support	26
3.5.1.4 Wake-up Control	26
4. Connector / Header Locations and Pin-outs	27
4.1 Board Connector Information	27
4.2 Power Connectors	27
4.3 I/O Connector Pin-out Definition	28
4.3.1 VGA Connector	28
4.3.2 I/O Mezzanine Card Connector	28
4.3.3 Midplane Signal Connector	29
4.3.4 Serial Port Connector	30
4.3.5 USB 2.0 Connectors	31
5. Jumper Block Settings	32
5.1 Recovery Jumper Blocks	32
5.1.1 CMOS Clear and Password Reset Usage Procedure	33
5.1.2 BMC Force Update Procedure	33
5.1.3 System Status LED – BMC Initialization	34
6. Product Regulatory Requirements	35
6.1 Product Regulatory Requirements	35
6.2 Product Regulatory Compliance and Safety Markings	35
6.3 Product Environmental/Ecology Requirements	35

Intel MFS2600KI Technical Product Specification - Page 36

Appendix A: Integration and Usage Tips

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