Intel Q9400S Data Sheet - Page 11

Introduction - performance

Page 11 highlights

Introduction 1 Note: Note: Introduction The Intel® Core™2 Extreme processor QX9000 series and Intel® Core™2 Quad processor Q9000, Q9000S, Q8000, and Q8000S series are based on the Enhanced Intel® Core™ microarchitecture. The Enhanced Intel Core microarchitecture combines the performance of previous generation Desktop products with the power efficiencies of a low-power microarchitecture to enable smaller, quieter systems. The Intel® Core™2 Extreme processor QX9000 series and Intel® Core™2 Quad processor Q9000, Q9000S, Q8000, and Q8000S series are 64-bit processors that maintains compatibility with IA32 software. The processors use a Flip-Chip Land Grid Array (FC-LGA6) package technology, and plugs into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the LGA775 socket. In this document, the Intel® Core™2 Extreme processor QX9000 series and the Intel® Core™2 Quad processor Q9000, Q9000S, Q8000, and Q8000S series may be referred to simply as "the processor." The following products are covered in this document: • The Intel® Core™2 Extreme processor QX9000 series refers to the QX9770 and QX9650. • The Intel® Core™2 Quad processor Q9000 series refers to the Q9650, Q9550, Q9505, Q9450, Q9400, and Q9300. • The Intel® Core™2 Quad processor Q9000S series refers to the Q9550S, Q9505S, and Q9400S. • The Intel® Core™2 Quad processor Q8000 series refers to the Q8200, Q8300, Q8400. • The Intel® Core™2 Quad processor Q8000S series refers to the Q8200S and Q8400S. The processor is based on 45 nm process technology. The processor features the Intel® Advanced Smart Cache, a shared multi-core optimized cache that significantly reduces latency to frequently used data. The processors feature 1600 MHz and 1333 MHz front side bus (FSB) frequencies.The processors also feature two independent but shared 12 MB of L2 cache (2x6M), two independent but shared 8 MB of L2 cache (2x4M), two independent but shared 6 MB of L2 cache (2x3M) or two independent but shared 4 MB of L2 caches (2x2M). The processor supports all the existing Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3), Supplemental Streaming SIMD Extension 3 (SSSE3), and the Streaming SIMD Extensions 4.1 (SSE4.1). The processor supports several Advanced Technologies: Execute Disable Bit, Intel® 64 architecture (Intel® 64), and Enhanced Intel SpeedStep® Technology. In addition, the Intel® Core™2 Extreme processor QX9000 series, Intel® Core™2 Quad processor Q9000 and Q9000S series, and Intel® Core™2 Quad processors Q8400 and Q8400S support Intel® Virtualization Technology (Intel® VT). Further, the Intel® Core™2 Quad processor Q9000 and Q9000S series support Intel® Trusted Execution Technology (Intel® TXT). The processor's front side bus (FSB) uses a split-transaction, deferred reply protocol. The FSB uses Source-Synchronous Transfer of address and data to improve performance by transferring data four times per bus clock (4X data transfer rate). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a "double-clocked" or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 12.4 GB/s. Datasheet 11

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Datasheet
11
Introduction
1
Introduction
The Intel
®
Core™2 Extreme processor QX9000 series and Intel
®
Core™2 Quad
processor Q9000, Q9000S, Q8000, and Q8000S series are based on the Enhanced
Intel
®
Core™ microarchitecture. The Enhanced Intel Core microarchitecture combines
the performance of previous generation Desktop products with the power efficiencies of
a low-power microarchitecture to enable smaller, quieter systems. The Intel
®
Core™2
Extreme processor QX9000 series and Intel
®
Core™2 Quad processor Q9000, Q9000S,
Q8000, and Q8000S series are 64-bit processors that maintains compatibility with IA-
32 software.
The processors use a Flip-Chip Land Grid Array (FC-LGA6) package technology, and
plugs into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the
LGA775 socket.
Note:
In this document, the Intel
®
Core™2 Extreme processor QX9000 series and the Intel
®
Core™2 Quad processor Q9000, Q9000S, Q8000, and Q8000S series may be referred
to simply as "the processor."
Note:
The following products are covered in this document:
The Intel
®
Core™2 Extreme processor QX9000 series refers to the QX9770 and
QX9650.
The Intel
®
Core™2 Quad processor Q9000 series refers to the Q9650, Q9550,
Q9505, Q9450, Q9400, and Q9300.
The Intel
®
Core™2 Quad processor Q9000S series refers to the Q9550S, Q9505S,
and Q9400S.
The Intel
®
Core™2 Quad processor Q8000 series refers to the Q8200, Q8300,
Q8400.
The Intel
®
Core™2 Quad processor Q8000S series refers to the Q8200S and
Q8400S.
The processor is based on 45 nm process technology. The processor features the Intel
®
Advanced Smart Cache, a shared multi-core optimized cache that significantly reduces
latency to frequently used data. The processors feature 1600 MHz and 1333 MHz front
side bus (FSB) frequencies.The processors also feature two independent but shared
12 MB of L2 cache (2x6M), two independent but shared 8 MB of L2 cache (2x4M), two
independent but shared 6 MB of L2 cache (2x3M) or two independent but shared 4 MB
of L2 caches (2x2M).
The processor supports all the existing Streaming SIMD Extensions 2 (SSE2),
Streaming SIMD Extensions 3 (SSE3), Supplemental Streaming SIMD Extension 3
(SSSE3), and the Streaming SIMD Extensions 4.1 (SSE4.1). The processor supports
several Advanced Technologies: Execute Disable Bit, Intel
®
64 architecture (Intel
®
64),
and Enhanced Intel SpeedStep
®
Technology. In addition, the Intel
®
Core™2 Extreme
processor QX9000 series, Intel
®
Core™2 Quad processor Q9000 and Q9000S series,
and Intel
®
Core™2 Quad processors Q8400 and Q8400S support Intel
®
Virtualization
Technology (Intel
®
VT). Further, the Intel
®
Core™2 Quad processor Q9000 and
Q9000S series support Intel
®
Trusted Execution Technology (Intel
®
TXT).
The processor's front side bus (FSB) uses a split-transaction, deferred reply protocol.
The FSB uses Source-Synchronous Transfer of address and data to improve
performance by transferring data four times per bus clock (4X data transfer rate).
Along with the 4X data bus, the address bus can deliver addresses two times per bus
clock and is referred to as a "double-clocked" or 2X address bus. Working together, the
4X data bus and 2X address bus provide a data bus bandwidth of up to 12.4 GB/s.