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Intel R2000WT Technical Product Specification - Page 27

Field Replaceable Unit FRU and Sensor Data Record SDR Data, Baseboard Management Controller BMC &amp

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Intel® Server Board S2600WT TPS Instructions provided with the system update package downloaded from the Intel web site. Once the update has completed, the recovery jumper is switched back to its default position and the system is power cycled. If the BIOS detects a partial BIOS update or the BMC asserts Recovery Mode GPIO, the BIOS will boot up with Recovery Mode. The difference is that the BIOS boots up to the Error Manager Page in the BIOS Setup utility. In the BIOS Setup utility, boot device, Shell or Linux for example, could be selected to perform the BIOS update procedure under Shell or OS environment. 2.3.2 Field Replaceable Unit (FRU) and Sensor Data Record (SDR) Data As part of the initial system integration process, the server board/system must have the proper FRU and SDR data loaded. This ensures that the embedded platform management system is able to monitor the appropriate sensor data and operate the system with best cooling and performance. The BMC supports automatic configuration of the manageability subsystem after changes have been made to the system's hardware configuration. Once the system integrator has performed an initial SDR/CFG package update, subsequent auto-configuration occurs without the need to perform additional SDR updates or provide other user input to the system when any of the following components are added or removed. • Processors • I/O Modules (dedicated slot modules) • Storage modules, such as a SAS module (dedicated slot modules) • Power supplies • Fans • Fan options (e.g. upgrade from non-redundant cooling to redundant cooling) • Intel® Xeon Phi™ co-processor cards • Hot Swap Backplane • Front Panel NOTE: The system may not operate with best performance or best/appropriate cooling if the proper FRU and SDR data is not installed. 2.3.2.1 Loading FRU and SDR Data The FRU and SDR data can be updated using a standalone FRUSDR utility in the uEFI shell, or can be done using the OFU utility program under a supported operating system. Full FRU and SDR update instructions are provided with the appropriate system update package (SUP) or OFU utility which can be downloaded from the Intel web site. 2.3.3 Baseboard Management Controller (BMC) & Management Engine (ME) Firmware See Chapters 7, 8, and 9 for features and functions associated with the BMC firmware and ME firmware. 13 Revision 1.0

Section	Page
1. Introduction	15
1.1 Chapter Outline	15
1.2 Server Board Use Disclaimer	15
2. Product Features Overview	16
2.1 Server Board Component/Feature Identification	18
2.2 Product Architecture Overview	22
2.3 System Software Overview	23
2.3.1 System BIOS	23
2.3.1.1 BIOS Revision Identification	24
2.3.1.2 Hot Keys Supported During POST	25
2.3.1.3 POST Logo/Diagnostic Screen	25
2.3.1.4 BIOS Boot Pop-Up Menu	25
2.3.1.5 Entering BIOS Setup	26
2.3.1.6 BIOS Update Capability	26
2.3.1.7 BIOS Recovery	26
2.3.2 Field Replaceable Unit (FRU) and Sensor Data Record (SDR) Data	27
2.3.2.1 Loading FRU and SDR Data	27
2.3.3 Baseboard Management Controller (BMC) & Management Engine (ME) Firmware	27
3. Processor Support	28
3.1 Processor Socket Assembly	28
3.2 Processor Thermal Design Power (TDP) Support	29
3.3 Processor Population Rules	29
3.4 Processor Initialization Error Summary	30
3.5 Processor Function Overview	32
3.5.1 Processor Core Features:	32
3.5.2 Supported Technologies:	32
3.5.2.1 Intel® Virtualization Technology (Intel® VT) for Intel® 64 and IA-32 Intel® Architecture (Intel® VT-x)	33
3.5.2.2 Intel® Virtualization Technology for Directed I/O (Intel® VT-d)	33
3.5.2.3 Intel® Trusted Execution Technology for servers (Intel® TXT)	33
3.5.2.4 Execute Disable Bit	33
3.5.2.5 Advanced Encryption Standard (AES)	33
3.5.2.6 Intel® Hyper-Threading Technology	33
3.5.2.7 Intel® Turbo Boost Technology	33
3.5.2.8 Enhanced Intel® SpeedStep Technology	33
3.5.2.9 Intel® Advanced Vector Extensions 2 (Intel® AVX2)	34
3.5.2.10 Intel® Node Manager 3.0	34
3.5.2.11 Intel® Secure Key	34
3.5.2.12 Intel® OS Guard	34
3.5.2.13 Trusted Platform Module (TPM)	34
4. System Memory	35
4.1 Memory Sub-system Architecture	35
4.2 IMC Modes of operation	36
4.3 Memory RASM Features	36
4.4 Supported Memory	37
4.5 NVDIMM Support	38
4.6 Memory Slot Identification and Population Rules	38
4.6.1 Memory Interleaving Support	41
4.6.2 NUMA Configuration Support	41
4.7 System Memory Sizing and Publishing	41
4.7.1 Effects of Memory Configuration on Memory Sizing	41
4.7.2 Publishing System Memory	42
4.8 Memory Initialization	43
4.8.1 DIMM Discovery	43
4.8.2 DIMM Population Validation Check	43
4.8.3 Channel Training	44
4.8.3.1 Thermal (CLTT) and power throttling	44
4.8.3.2 Built-In Self Test (BIST)	44
4.8.3.3 RAS Mode Initialization	45
5. System I/O	46
5.1 PCIe* Support	46
5.2 PCIe* Enumeration and Allocation	47
5.3 PCIe* Non-Transparent Bridge (NTB)	47
5.4 Add-in Card Support	48
5.4.1 Riser Card Support	49
5.4.2 I/O Module Support	52
5.4.3 Intel® Integrated RAID Option	53
5.5 Serial ATA (SATA) Support	54
5.5.1 Staggered Disk Spin-Up	56
5.6 Embedded SATA SW-RAID support	56
5.6.1 Intel® Rapid Storage Technology (RSTe) 4.0	56
5.6.2 Intel® Embedded Server RAID Technology 2 (ESRT2)	57
5.7 Network Interface	58
5.7.1 Intel® Ethernet Controller Options	59
5.7.2 Factory Programmed MAC Address Assignments	59
5.8 Video Support	59
5.8.1 Dual Video and Add-In Video Adapters	60
5.8.1.1 Dual Monitor Video	61
5.8.1.2 Configuration Cases – Multi-CPU Socket Boards and Add-In Video Adapters	61
5.8.2 Setting Video Configuration Options using the BIOS Setup Utility	62
5.9 USB Support	64
5.9.1 Low Profile eUSB SSD Support	64
5.10 Serial Ports	65
6. System Security	67
6.1 BIOS Setup Utility Security Options Menu	67
6.1.1 Password Setup	67
6.1.2 System Administrator Password Rights	68
6.1.3 Authorized System User Password Rights and Restrictions	68
6.1.4 Front Panel Lockout	68
6.2 Trusted Platform Module (TPM) Support	69
6.2.1 TPM security BIOS	69
6.2.2 Physical Presence	70
6.2.3 TPM Security Setup Options	70
6.3 Intel® Trusted Execution Technology	71
7. Platform Management	72
7.1 Management Feature Set Overview	72
7.1.1 IPMI 2.0 Features Overview	72
7.1.2 Non IPMI Features Overview	73
7.2 Platform Management Features and Functions	75
7.2.1 Power Sub-system	75
7.2.2 Advanced Configuration and Power Interface (ACPI)	75
7.2.3 System Initialization	75
7.2.3.1 Processor Tcontrol Setting	75
7.2.3.2 Fault Resilient Booting (FRB)	76
7.2.3.3 Post Code Display	76
7.2.4 Watchdog Timer	76
7.2.5 System Event Log (SEL)	76
7.3 Sensor Monitoring	76
7.3.1 Sensor Scanning	77
7.3.2 Sensor Rearm Behavior	77
7.3.2.1 Manual versus Re-arm Sensors	77
7.3.2.2 Re-arm and Event Generation	77
7.3.3 BIOS Event-Only Sensors	78
7.3.4 Margin Sensors	78
7.3.5 IPMI Watchdog Sensor	78
7.3.6 BMC Watchdog Sensor	78
7.3.7 BMC System Management Health Monitoring	78
7.3.8 VR Watchdog Timer	78
7.3.9 System Airflow Monitoring	78
7.3.10 Thermal Monitoring	79
7.3.10.1 Absolute Value versus Margin Sensors	79
7.3.10.2 Processor DTS-Spec Margin Sensor(s)	79
7.3.10.3 Processor Thermal Margin Sensor(s)	79
7.3.10.4 Processor Thermal Control Monitoring (Prochot)	80
7.3.10.5 Processor Voltage Regulator (VRD) Over-Temperature Sensor	80
7.3.10.6 Inlet Temperature Sensor	80
7.3.10.7 Baseboard Ambient Temperature Sensor(s)	80
7.3.10.8 Server South Bridge (SSB) Thermal Monitoring	80
7.3.10.9 Exit Air Temperature Monitoring	81
7.3.10.10 Ethernet Controller Thermal Monitoring	81
7.3.10.11 Memory VRD-Hot Sensor(s)	81
7.3.10.12 Add-in Module Thermal Monitoring	81
7.3.10.13 Processor ThermTrip	81
7.3.10.14 Server South Bridge (SSB) ThermTrip Monitoring	81
7.3.10.15 DIMM ThermTrip Monitoring	81
7.3.11 Processor Sensors	82
7.3.11.1 Processor Status Sensors	82
7.3.11.2 Processor Population Fault (CPU Missing) Sensor	82
7.3.11.3 ERR2 Timeout Monitoring	83
7.3.11.4 CATERR Sensor	83
7.3.11.5 MSID Mismatch Sensor	84
7.3.12 Voltage Monitoring	84
7.3.12.1 Discrete Voltage Sensors	84
7.3.13 Fan Monitoring	84
7.3.13.1 Fan Tach Sensors	84
7.3.13.2 Fan Presence Sensors	85
7.3.13.3 Fan Redundancy Sensor	85
7.3.13.4 Power Supply Fan Sensors	85
7.3.13.5 Monitoring for “Fans Off” Scenario	85
7.3.14 Standard Fan Management	86
7.3.14.1 Hot-Swap Fans	86
7.3.14.2 Fan Redundancy Detection	87
7.3.14.3 Fan Domains	87
7.3.14.4 Nominal Fan Speed	87
7.3.14.5 Thermal and Acoustic Management	88
7.3.14.6 Thermal Sensor Input to Fan Speed Control	88
7.3.14.6.1 Processor Thermal Management	89
7.3.14.6.2 Memory Thermal Management	89
7.3.14.6.2.1 Memory Thermal Throttling	89
7.3.14.6.3 DIMM Temperature Sensor Input to Fan Speed Control	90
7.3.14.6.4 Dynamic (Hybrid) CLTT	90
7.3.14.6.5 Fan Profiles	91
7.3.14.6.6 Open-Loop Thermal Throttling Fallback	91
7.3.14.6.7 ASHRAE Compliance	91
7.3.14.7 Power Supply Fan Speed Control	91
7.3.14.7.1 System Control of Power Supply Fans	91
7.3.14.7.2 Use of Power Supply Thermal Sensors as Input to System (Chassis) Fan Control	92
7.3.14.8 Fan Boosting due to Fan Failures	92
7.3.14.9 Programmable Fan PWM Offset	92
7.3.15 Power Management Bus (PMBus*)	92
7.3.16 Power Supply Dynamic Redundancy Sensor	92
7.3.17 Component Fault LED Control	93
7.3.18 NMI (Diagnostic Interrupt) Sensor	94
7.3.19 LAN Leash Event Monitoring	94
7.3.20 Add-in Module Presence Sensor	94
7.3.21 CMOS Battery Monitoring	94
8. Intel® Intelligent Power Node Manager (NM) Support Overview	95
8.1 Hardware Requirements	95
8.2 Features	95
8.3 ME System Management Bus (SMBus*) interface	95
8.4 PECI 3.0	96
8.5 NM “Discovery” OEM SDR	96
8.6 SmaRT/CLST	96
8.6.1 Dependencies on PMBus*-compliant Power Supply Support	97
9. Basic and Advanced Server Management Features	98
9.1 Dedicated Management Port	99
9.2 Embedded Web Server	99
9.3 Advanced Management Feature Support (RMM4 Lite)	101
9.3.1 Keyboard, Video, Mouse (KVM) Redirection	101
9.3.2 Remote Console	102
9.3.3 Performance	102
9.3.4 Security	103
9.3.5 Availability	103
9.3.6 Usage	103
9.3.7 Force-enter BIOS Setup	103
9.3.8 Media Redirection	103
9.3.8.1 Availability	104
9.3.8.2 Network Port Usage	104
10. On-board Connector/Header Overview	105
10.1 Power Connectors	105
10.1.1 Main Power	105
10.1.2 Hot Swap Backplane Power Connector	106
10.1.3 Peripheral Drive Power Connector	107
10.1.4 Riser Card Supplemental 12V Power Connectors	107
10.2 Front Panel Headers and Connectors	108
10.2.1 Front Panel Button and LED Support	108
10.2.2 Front Panel LED and Control Button Features Overview	109
10.2.2.1 Power/Sleep Button and LED Support	109
10.2.2.2 System ID Button and LED Support	109
10.2.2.3 System Reset Button Support	109
10.2.2.4 NMI Button Support	109
10.2.2.5 NIC Activity LED Support	110
10.2.2.6 Storage Device Activity LED Support	110
10.2.2.7 System Status LED Support	110
10.2.3 Front Panel USB 2.0 Connector	110
10.2.4 Front Panel USB 3.0 Connector	111
10.2.5 Front Panel Video Connector	111
10.2.6 Intel® Local Control Panel Connector	111
10.3 On-Board Storage Option Connectors	112
10.3.1 Single Port SATA Only Connectors	112
10.3.1.1 SATA SGPIO Connector	112
10.3.2 Internal Type-A USB Connector	113
10.3.3 Internal 2mm Low Profile eUSB SSD Connector	113
10.4 System Fan Connectors	114
10.5 Other Connectors and Headers	115
10.5.1 Chassis Intrusion Header	115
10.5.2 Storage Device Activity LED Header	115
10.5.3 Intelligent Platform Management Bus (IPMB) Connector	115
10.5.4 Hot Swap Backplane I2C* Connectors	116
10.5.5 SMBus Connector	116
11. Reset and Recovery Jumpers	117
11.1 BIOS Default Jumper Block	117
11.2 Serial Port ‘A’ Configuration Jumper	118
11.3 Password Clear Jumper Block	118
11.4 Management Engine (ME) Firmware Force Update Jumper Block	118
11.5 BMC Force Update Jumper Block	119
11.6 BIOS Recovery Jumper	120
12. Light Guided Diagnostics	121
12.1 System ID LED	122
12.2 System Status LED	122
12.3 BMC Boot/Reset Status LED Indicators	125
12.4 Post Code Diagnostic LEDs	125
12.5 Fan Fault LEDs	125
12.6 Memory Fault LEDs	125
12.7 CPU Fault LEDs	125
13. Power Supply Specification Guidelines	126
13.1 Power Supply DC Output Connector	126
13.2 Power Supply DC Output Specification	127
13.2.1 Output Power/Currents	127
13.2.2 Standby Output	127
13.2.3 Voltage Regulation	127
13.2.4 Dynamic Loading	127
13.2.5 Capacitive Loading	128
13.2.6 Grounding	128
13.2.7 Closed loop stability	128
13.2.8 Residual Voltage Immunity in Standby mode	128
13.2.9 Common Mode Noise	128
13.2.10 Soft Starting	128
13.2.11 Zero Load Stability Requirements	128
13.2.12 Hot Swap Requirements	128
13.2.13 Forced Load Sharing	128
13.2.14 Ripple/Noise	129
13.2.15 Timing Requirements	129
14.	130
Appendix A: Integration and Usage Tips	131
Appendix B: Integrated BMC Sensor Tables	132
Appendix C: Management Engine Generated SEL Event Messages	146
Appendix D: POST Code Diagnostic LED Decoder	148
Appendix E: POST Code Errors	155

Match case Limit results 1 per page

Intel® Server Board S2600WT TPS

Revision 1.0

Instructions provided with the system update package downloaded from the Intel web site. Once the update

has completed, the recovery jumper is switched back to its default position and the system is power cycled.

If the BIOS detects a partial BIOS update or the BMC asserts Recovery Mode GPIO, the BIOS will boot up with

Recovery Mode. The difference is that the BIOS boots up to the Error Manager Page in the BIOS Setup utility.

In the BIOS Setup utility, boot device, Shell or Linux for example, could be selected to perform the BIOS

update procedure under Shell or OS environment.

2.3.2

Field Replaceable Unit (FRU) and Sensor Data Record (SDR) Data

As part of the initial system integration process, the server board/system must have the proper FRU and SDR

data loaded.

This ensures that the embedded platform management system is able to monitor the

appropriate sensor data and operate the system with best cooling and performance.

The BMC supports

automatic configuration of the manageability subsystem after changes have been made to the system’s

hardware configuration.

Once the system integrator has performed an initial SDR/CFG package update,

subsequent auto-configuration occurs without the need to perform additional SDR updates or provide other

user input to the system when any of the following components are added or removed.

•

Processors

•

I/O Modules (dedicated slot modules)

•

Storage modules, such as a SAS module (dedicated slot modules)

•

Power supplies

•

Fans

•

Fan options (e.g. upgrade from non-redundant cooling to redundant cooling)

•

Intel® Xeon Phi™ co-processor cards

•

Hot Swap Backplane

•

Front Panel

NOTE:

The system may not operate with best performance or best/appropriate cooling if the proper FRU

and SDR data is not installed.

2.3.2.1

Loading FRU and SDR Data

The FRU and SDR data can be updated using a standalone FRUSDR utility in the uEFI shell, or can be done

using the OFU utility program under a supported operating system. Full FRU and SDR update instructions are

provided with the appropriate system update package (SUP) or OFU utility which can be downloaded from

the Intel web site.

2.3.3

Baseboard Management Controller (BMC) & Management Engine (ME) Firmware

See Chapters 7, 8, and 9 for features and functions associated with the BMC firmware and ME firmware.