Intel SL79K Specification Update - Page 49

VERR/VERW Instructions May Cause #GP Fault When Descriptor Is in Non

Get Intel SL79K - Pentium 4 2.80GHz 800MHz 1MB Socket 478 CPU PDF manuals and user guides
UPC - 683728144456
View all Intel SL79K manuals
Add to My Manuals
Save this manual to your list of manuals

Page 49 highlights

Errata R R52. Incorrect Access Controls to MSR_LASTBRANCH_0_FROM_LIP MSR Registers Problem: When an access is made to the MSR_LASTBRANCH_0_FROM_LIP MSR register, an expected #GP fault may not happen. Implication: A read of the MSR_LASTBRANCH_0_FROM_LIP MSR register may not cause a #GP fault. Workaround: It is possible for the BIOS to contain a workaround for this erratum Status: For the steppings affected, see the Summary Tables of Changes. R53. Recursive Page Walks May Cause a System Hang Problem: A page walk, accessing the same page table entry multiple times but at different levels of the page table, which causes the page table entry to have its Access bit set may result in a system hang. Implication: When this erratum occurs, the system may experience a hang. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. R54. WRMSR to bit[0] of IA32_MISC_ENABLE Register Changes Only One Logical Processor on a Hyper-Threading Technology Enabled Processor Problem: On an HT enabled processor, a write to the fast-strings feature bit[0] of IA32_MISC_ENABLE register changes the setting for the current logical processor only. Implication: Due to this erratum, the non-current logical processor may not update fast-strings feature bit[0] of IA32_MISC_ENABLE register. Workaround: BIOS may set the fast-strings enable bit on both logical processors to workaround this erratum. It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. R55. VERR/VERW Instructions May Cause #GP Fault When Descriptor Is in Noncanonical Space Problem: If a descriptor referenced by the selector specified for the VERR or VERW instructions is in noncanonical space, it may incorrectly cause a #GP fault on a processor supporting Intel® Extended Memory 64 Technology (Intel® EM64T). Implication: Operating systems or drivers that reference a selector in non-canonical space may experience an unexpected #GP fault. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Pentium® 4 Processor on 90 nm Process Specification Update 49

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
Errata
R
Intel
®
Pentium
®
4 Processor on 90 nm Process Specification Update
49
R52.
Incorrect Access Controls to MSR_LASTBRANCH_0_FROM_LIP MSR
Registers
Problem:
When an access is made to the MSR_LASTBRANCH_0_FROM_LIP MSR register, an expected
#GP fault may not happen.
Implication:
A read of the MSR_LASTBRANCH_0_FROM_LIP MSR register may not cause a #GP fault.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum
Status:
For the steppings affected, see the
Summary Tables of Changes
.
R53.
Recursive Page Walks May Cause a System Hang
Problem:
A page walk, accessing the same page table entry multiple times but at different levels of the page
table, which causes the page table entry to have its Access bit set may result in a system hang.
Implication:
When this erratum occurs, the system may experience a hang.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
R54.
WRMSR to bit[0] of IA32_MISC_ENABLE Register Changes Only One
Logical Processor on a Hyper-Threading Technology Enabled Processor
Problem:
On an HT enabled processor, a write to the fast-strings feature bit[0] of IA32_MISC_ENABLE
register changes the setting for the current logical processor only.
Implication:
Due to this erratum, the non-current logical processor may not update fast-strings feature bit[0] of
IA32_MISC_ENABLE register.
Workaround:
BIOS may set the fast-strings enable bit on both logical processors to workaround this erratum. It
is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
R55.
VERR/VERW Instructions May Cause #GP Fault When Descriptor Is in Non-
canonical Space
Problem:
If a descriptor referenced by the selector specified for the VERR or VERW instructions is in non-
canonical space, it may incorrectly cause a #GP fault on a processor supporting Intel
®
Extended
Memory 64 Technology (Intel
®
EM64T).
Implication:
Operating systems or drivers that reference a selector in non-canonical space may experience an
unexpected #GP fault.
Intel has not observed this erratum with any commercially available
software.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes
.